参数资料
| 型号： | ISL6563CR-T |
| 厂商： | Intersil |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM MULTIPHASE 24-QFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 1.85 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 带卷 (TR) |
ISL6563
R ISEN = ----------------------- ? --------
r DS ( ON ) I FL
50 × 10 – 6
P UMOS , 1 ≈ V IN ? ------------- + ------------- ? ? ---- 1 ? f S
V DROOP ? 2 ? R ISEN
R 1 = -------------------------------------------------------
? I OUT I L , PP ? ? ?
P UMOS , 2 ≈ V IN ? ------------- – ------------- ? ? ---- 2 ? f S
(EQ. 13)
The above equation assumes the current through the lower
MOSFET is always positive; if so, the total power dissipated
in each lower MOSFET is approximated by the summation of
P LMOS1 and P LMOS2 .
UPPER MOSFET POWER CALCULATION
In addition to r DS(ON) losses, a large portion of the upper-
MOSFET losses are switching losses, due to currents
conducted through the device while the input voltage is
present as V DS . Upper MOSFET losses can be divided into
separate components, separating the upper-MOSFET
switching losses, the lower-MOSFET body diode reverse
recovery charge loss, and the upper MOSFET r DS(ON)
conduction loss.
In most typical circuits, when the upper MOSFET turns off, it
continues to conduct the inductor current until the voltage at
the phase node falls below ground. Once the lower
MOSFET begins conducting (via its body diode or
enhancement channel), the current in the upper MOSFET
falls to zero. In Equation 12, the required time for this
commutation is t 1 and the associated power loss is P UMOS,1 .
? I OUT I L , PP ? ? t ? (EQ. 12)
? 2 2 ? ? 2 ?
Similarly, the upper MOSFET begins conducting as soon as
it begins turning on. Assuming the inductor current is in the
positive domain, the upper MOSFET sees approximately the
input voltage applied across its drain and source terminals,
while it turns on and starts conducting the inductor current.
This transition occurs over a time t 2 , and the approximate
the power loss is P UMOS,2 .
t
? 2 2 ? ? 2 ?
A third component involves the lower MOSFET’s reverse-
recovery charge, Q RR . Since the lower MOSFET’s body
diode conducts the full inductor current before it has fully
switched to the upper MOSFET, the upper MOSFET has to
provide the charge required to turn off the lower MOSFET’s
body diode. This charge is conducted through the upper
MOSFET across VIN, the power dissipated as a result,
P UMOS,3 can be approximated using Equation 14:
Since the power equations depend on MOSFET parameters,
choosing the correct MOSFETs can be an iterative process
that involves repetitively solving the loss equations for
different MOSFETs and different switching frequencies until
converging upon the best solution.
Current Sensing
The resistor connected between the ISEN and VCC pins
determines the gain in the load-line regulation and the
channel-current balance loop. Select the value for this
resistor based on the room temperature r DS(ON) of the lower
MOSFETs and the full-load total output current, I FL .
(EQ. 16)
2
Load Line Regulation Resistor
The load-line regulation resistor is labeled, R1 in Figure 1,
depends on the desired full-load droop voltage. At full load,
the current determined by R ISEN is fed into the FB pin and
creates the output voltage droop across R1. Thus, the load
line regulation resistor can be computed using Equation 17:
(EQ. 17)
r DS ( ON ) ? I FL
Frequency Compensation
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output filter LC resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R 2 and C 2 .
The solution to the system equations can be fairly
complicated. Fortunately, there is a simple approximation
that comes very close to an optimal solution. Treating the
system as though it were a voltage mode regulator by
compensating the LC poles and the ESR zero of the voltage
mode approximation yields a solution that is always stable
with very close to ideal transient performance.
C 1
P UMOS , 3 = V IN Q rr f S
(EQ. 14)
R 2
C 2
COMP
Lastly, the conduction loss part of the upper MOSFET’s
power dissipation, P UMOS,4, can be calculated using
Equation 15:
FB
I PP2
? I OUT ?
P UMOS , 4 = r DS ( ON ) ? ------------- ? d + ----------
2
? 2 ? 12
(EQ. 15)
R 1
+
V DROOP
-
In this case, of course, r DS(ON) is the ON-resistance of the
upper MOSFET.
The total power dissipated by the upper MOSFET at full load
can be approximated as the summation of these results.
14
V OUT
FIGURE 8. COMPENSATION CONFIGURATION FOR ISL6563
CIRCUIT
FN9126.8
June 10, 2010
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6563CR-TK | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL6563CRZ | 功能描述:电流型 PWM 控制器 P6 TWO PHS CONT INTEGRTD DRVRS DESKT RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6563CRZ-T | 功能描述:电流型 PWM 控制器 P6 TWO PHS CONT INTEGRTD DRVRS DESKT RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6563CRZ-TK | 功能描述:IC CTRLR PWM MULTIPHASE 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6563EVAL1 | 制造商:Intersil Corporation 功能描述:DEV TOOLS, EVAL BD - Bulk 制造商:Intersil 功能描述:ISL6563 EVALRD |
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