参数资料
| 型号： | ISL6563IR-T |
| 厂商： | Intersil |
| 文件页数： | 6/19页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM MULTIPHASE 24-QFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 1.85 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 带卷 (TR) |
ISL6563
Functional Pin Description
VCC (Pin 8)
Bias supply for the IC’s small-signal circuitry. Connect this
pin to a 5V supply and locally decouple using a quality 0.1μF
ceramic capacitor.
PVCC (Pin 16)
Power supply pin for the MOSFET drives. Connect this pin to
a 5V supply and locally decouple using a quality 1μF
ceramic capacitor.
ISEN (Pin 7)
This pin is used to close the current-feedback loop and set the
overcurrent protection threshold. A resistor connected between
this pin and VCC has a voltage drop forced across it equal to
that sampled across the lower MOSFET’s r DS(ON) during
approximately the middle of its conduction interval. The
resulting current through this resistor is used for channel
current balancing, overcurrent protection and is sourced to the
FB pin for load-line regulation. The voltage across the R ISEN
resistor is time multiplexed between the two channels.
GND and PGND (Pins 25 and 14)
Connect these pins to the circuit ground using the shortest
possible paths. All internal small-signal circuitry is
referenced to the GND pin. LGATE drive is referenced to the
Use Equation 1 to select the proper R ISEN resistor:
50 μ A
r DS ( ON ) × I OUT
R ISEN = ------------------------------------------
where:
(EQ. 1)
PGND pin.
VID0-4 (Pins 2, 1, 24-22)
Voltage identification inputs from microprocessor. These pins
respond to TTL logic thresholds. The ISL6563 decodes the
VID inputs to establish the output voltage; see VID Tables for
correspondence between DAC codes and output voltage
settings. These pins are internally pulled high, to
approximately 1.2V, by 40μA (typically) internal current
sources; the internal pull-up current decrease to 0 as the VID
voltage approaches the internal pull-up voltage. All VID pins
are compatible with external pull-up voltages not exceeding
the IC’s bias voltage.
DACSEL/VID5 (Pin 3)
If VRM10 pin is grounded, DACSEL/VID5 represents the 6th
voltage identification input from the VRM10-compliant
microprocessor, otherwise known as VID5. If VRM10 pin is
open or pulled high, DACSEL/VID5 selects the compliance
standard for the internal DAC: pulled to ground it encodes the
DAC with AMD Hammer VID codes, while left open or pulled
high, it encodes the DAC with Intel VRM9.0 codes.
VRM10 (Pin 4)
This pin selects VRM10.0 DAC compliance when grounded.
Left open, it allows selection of either VRM9.0 or Hammer
DAC compliance via DACSEL pin.
ENLL (Pin 21)
This pin is a precision-threshold (approximately 0.6V) enable
pin. Held low, this pin disables controller operation. Pulled
r DS(ON) = lower MOSFET drain-source ON-resistance ( Ω )
I OUT = channel maximum output current (A)
Read ‘Current Feedback’ paragraph for more information.
UGATE1, 2 (Pins 19, 12)
Connect these pins to the upper MOSFETs’ gates. These
pins are used to control the upper MOSFETs and are
monitored for shoot-through prevention purposes. Maximum
individual channel duty cycle is limited to 66%.
BOOT1, 2 (Pins 20, 11)
These pins provide the bias voltage for the upper MOSFETs’
drives. Connect these pins to appropriately-chosen external
bootstrap capacitors. Internal bootstrap diodes connected to
the PVCC pins provide the necessary bootstrap charge.
PHASE1, 2 (Pins 18, 13)
Connect these pins to the sources of the upper MOSFETs.
These pins are the return path for the upper MOSFETs’ drives.
LGATE1, 2 (Pins 17, 15)
These pins are used to control the lower MOSFETs and are
monitored for shoot-through prevention purposes. Connect
these pins to the lower MOSFETs’ gates.
OFS (Pin 9)
This pin is used to create an adjustable output voltage offset.
For no offset, leave this pin open. For negative offset, connect
an R’ OFS resistor from this pin to VCC and size it according to
Equation 2:
R ′ OFS = R 1 × --------------------------
V
high, the pin enables the controller for operation.
FB and COMP (Pins 6, 5)
1500
OFFSET
(EQ. 2)
(EQ. 3)
R OFS = R 1 × --------------------------
V
The internal error amplifier ’s inverting input and output
respectively. These pins are connected to the external
network used to compensate the regulator ’s feedback loop.
An internal current source injects the average current
sampled through R ISEN into the FB pin. Pulling COMP to
ground through an impedance lower than 15 Ω disables the
controller (same effect as ENLL pulled low).
6
where:
V OFFSET = desired output voltage offset magnitude (mV)
For positive output voltage offset, connect an R OFS resistor
from this pin to GND, sizing it according to Equation 3:
500
OFFSET
FN9126.8
June 10, 2010
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| ISL6563IRZ | 功能描述:电流型 PWM 控制器 P6 TWO PHS CONT INTEGRTD DRVRS DESKT RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6563IRZ-T | 功能描述:电流型 PWM 控制器 P6 TWO PHS CONT INTEGRTD DRVRS DESKT RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6564ACRZ | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6564ACRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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