参数资料
型号: ISL6609AIRZ-TK
厂商: Intersil
文件页数: 9/12页
文件大小: 0K
描述: IC MOSFET DVR SYNC RECT 8-QFN
标准包装: 1
配置: 高端和低端,同步
输入类型: PWM
延迟时间: 18ns
电流 - 峰: 2A
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 36V
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-VQFN 裸露焊盘
供应商设备封装: 8-QFN(3x3)
包装: 标准包装
产品目录页面: 1248 (CN2011-ZH PDF)
其它名称: ISL6609AIRZ-TKDKR
ISL6609, ISL6609A
VCC
BOOT
C GD
D
Layout Considerations
A good layout helps reduce the ringing on the switching
node (PHASE) and significantly lower the stress applied to
the output drives. The following advice is meant to lead to an
R HI1
G
C DS
optimized layout:
R LO1
UGATE
R G1
R GI1
C GS
Q1
? Keep decoupling loops (VCC-GND and BOOT-PHASE) as
short as possible.
PHASE
S
? Minimize trace inductance, especially on low-impedance
lines. All power traces (UGATE, PHASE, LGATE, GND,
VCC) should be short and wide, as much as possible.
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
? Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
VCC
D
? Minimize the current loop of the output and input power
trains. Short the source connection of the lower MOSFET
R HI2
R LO2
LGATE
GND
G
R G2
C GD
R GI2
C GS
S
C DS
Q2
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be
placed as close to the drain of upper and source of lower
MOSFETs as possible.
In addition, connecting the thermal pad of the QFN package
to the power ground through a via, or placing a low noise
copper plane underneath the SOIC part is recommended for
high switching frequency, high current applications. This is to
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Application Information
MOSFET and Driver Selection
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs) can
cause serious ringing, exceeding absolute maximum rating
of the devices. The negative ringing at the edges of the
PHASE node could increase the bootstrap capacitor voltage
through the internal bootstrap diode, and in some cases, it
may overstress the upper MOSFET driver. Careful layout,
proper selection of MOSFETs and packaging, as well as the
proper driver can go a long way toward minimizing such
unwanted stress.
The selection of D 2 -PAK, or D-PAK packaged MOSFETs, is a
much better match (for the reasons discussed) for the
ISL6609A. Low-profile MOSFETs, such as Direct FETs and
multi-SOURCE leads devices (SO-8, LFPAK, PowerPAK),
have low parasitic lead inductances and can be driven by
either ISL6609 or ISL6609A (assuming proper layout design).
The ISL6609, missing the 3 Ω integrated BOOT resistor,
improve heat dissipation and allow the part to achieve its
full thermal potential.
Upper MOSFET Self Turn-On Effects at Startup
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, because of
self-coupling via the internal C GD of the MOSFET, the
UGATE could momentarily rise up to a level greater than the
threshold voltage of the MOSFET. This could potentially turn
on the upper switch and result in damaging inrush energy.
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is a common practice to
place a resistor (R UGPH ) across the gate and source of the
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the C GD /C GS ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
C DS /C GS ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, a
5k to 10k Ω resistor is typically sufficient, not affecting normal
performance and efficiency.
typically yields slightly higher efficiency than the ISL6609A.
The coupling effect can be roughly estimated with the
following equations, which assume a fixed linear input ramp
and neglect the clamping effect of the body diode of the
upper drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purpose only.
9
FN9221.2
April 27, 2009
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ISL6609CBZ-T 功能描述:IC MOSFET DRVR SYNC BUCK 8-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET,电桥驱动器 - 外部开关 系列:- 标准包装:5 系列:- 配置:低端 输入类型:非反相 延迟时间:600ns 电流 - 峰:12A 配置数:1 输出数:1 高端电压 - 最大(自引导启动):- 电源电压:14.2 V ~ 15.8 V 工作温度:-20°C ~ 60°C 安装类型:通孔 封装/外壳:21-SIP 模块 供应商设备封装:模块 包装:散装 配用:BG2A-NF-ND - KIT DEV BOARD FOR IGBT 其它名称:835-1063
ISL6609CRZ 功能描述:IC MOSFET DRVR SYNC BUCK 8-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET,电桥驱动器 - 外部开关 系列:- 标准包装:5 系列:- 配置:低端 输入类型:非反相 延迟时间:600ns 电流 - 峰:12A 配置数:1 输出数:1 高端电压 - 最大(自引导启动):- 电源电压:14.2 V ~ 15.8 V 工作温度:-20°C ~ 60°C 安装类型:通孔 封装/外壳:21-SIP 模块 供应商设备封装:模块 包装:散装 配用:BG2A-NF-ND - KIT DEV BOARD FOR IGBT 其它名称:835-1063
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