参数资料
| 型号： | ISL6617IRZ |
| 厂商： | Intersil |
| 文件页数： | 12/15页 |
| 文件大小： | 0K |
| 描述： | IC PWM DOUBLER MONITOR 10DFN |
| 标准包装： | 100 |
| 应用： | PWM Doubler |
| 电流 - 电源： | 6mA |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
ISL6617
I SEN = I L ? ------------------
(EQ. 4)
R SENSE V OUT
resistor R ISEN . Therefore, the current out of ISEN+ pin,
I SEN , is proportional to the inductor current.
Because of the internal filter at ISEN- pin, one capacitor,
C T , is needed to match the time delay between the ISEN-
and ISEN+ signals. Select the proper C T to keep the time
constant of R ISEN and C T (R ISEN x C T ) close to 27ns.
Equation 4 shows that the ratio of the channel current to
the sensed current, I SEN , is driven by the value of the
sense resistor and the DCR of the inductor.
DCR
R ISEN
B. RESISTIVE SENSING
For more accurate current sensing, a dedicated resistor
R SENSE in series with each output inductor can serve as
the current sense element (see Figure 11). This
technique reduces overall converter efficiency due to the
additional power loss on the current sense element
R SENSE .
IL
L
C OUT
ISL6617
current balance, the power loss is equally dissipated over
multiple devices and a greater area.
The resulting average current I AVG also goes out from
the IOUT pin for current monitoring and can also be fed
back to the controller’s ISEN lines for current balance,
load-line regulation, and overcurrent protection. For fast
response to the current information, the IOUT pin should
have minimum decoupling; no more than 50ns filter is
recommended. The full scale of IOUT is 100 μA ; it
typically should set resistor gain around 50μA to 80 μA at
the full load to ensure that it will not hit the full scale
prior to the overcurrent trip point. At the same time, the
current signal accuracy is maximized.
Benefits of a High Phase Count System
At heavy load condition, efficiency can be improved by
spreading the load across many phases. This is primarily
because the resistive loss becomes the dominant
component of total loss budget at high current levels.
Since the load is carried by more phases, each power
device handles less current. In addition, the devices are
likely to be spread over a larger area on the Printed
Circuit Board (PCB). Both these factors result in
improved heat dissipation for higher phase count
systems. By reducing the system’s operating
I A/B
R ISEN(A/B)
temperature, components reliability is improved.
Furthermore, increasing the phase count also reduces
CURRENT
SENSE
+
-
ISEN-(A/B)
ISEN+(A/B)
C T
the size of ripple on both the input and output currents.
It reduces EMI and improves the efficiency. Figures 12
and 13 show the ripple values for a 24-Phase voltage
regulator with the following parameters:
? Input voltage: 12V
SENSE
I SEN = I --------------------------
L R
I SEN = I L ? -----------------------
R
R
ISEN
FIGURE 11. SENSE RESISTOR IN SERIES WITH
INDUCTORS
The same capacitor C T is needed to match the time
delay between ISEN- and ISEN+ signals. Select the
proper C T to keep the time constant of R ISEN and C T
(R ISEN x C T ) close to 27ns.
Equation 5 shows the ratio of the channel current to the
sensed current I SEN .
R SENSE (EQ. 5)
ISEN
Current Balance and Current Monitoring
The sensed currents I A and I B from each respective
channel are summed together and divided by 2. The
resulting average current I AVG provides a measure of the
total load current. Channel current balance is achieved
by comparing the sensed current of each channel to the
? Output voltage: 1.6V
? Duty cycle: 13.3%
? Load current: 200A
? Output Phase Inductor: 500nH
? Phase switching frequency: 200kHz
In this example, the 24-phase voltage regulator (VR) can
run in 6-phase, 8-phase, 12-phase, 24-phase
interleaving mode. In 6-phase interleaving mode, every
4 phases runs synchronously, which yields 18.73A and
12.93A input and output ripple currents, respectively.
The 24-phase interleaving regulator significantly drops
these values to 4.05A and 0.78A, respectively. As shown
in Table 3, both input and output ripple currents are
reduced when more phases are running in interleaving
mode. Note that the 8-phase VR has lower output ripple
current than the 12-phase VR since the 8-phase VR has
better output ripple cancellation factor close to the duty
cycle of 1/8.
TABLE 3. RIPPLE CURRENT (UNIT: A)
average current to make an appropriate adjustment to
the PWMA and PWMB duty cycle with Intersil’s patented
current-balance method.
Channel current balance is essential in achieving the
INTERLEAVED PHASES
Input Ripple Current
Output Ripple Current
6
18.73
12.93
8
11.64
2.70
12
8.79
4.83
24
4.05
0.78
thermal advantage of multiphase operation. With good
12
FN7564.0
February 4, 2010
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