参数资料
| 型号： | ISL6617IRZ |
| 厂商： | Intersil |
| 文件页数： | 9/15页 |
| 文件大小： | 0K |
| 描述： | IC PWM DOUBLER MONITOR 10DFN |
| 标准包装： | 100 |
| 应用： | PWM Doubler |
| 电流 - 电源： | 6mA |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
ISL6617
C. VARIOUS OPERATIONAL MODES
The ISL6617 has three distinct operating modes
depending upon the voltage level of the EN_PH_SYNC
pin. To ensure that the ISL6617 is in operation, the pin
must be above 2V. When the EN_PH_SYNC pin is set to
above 97% of V CC , the ISL6617 will operate in
interleaving mode with a maximum extension of 70ns.
When V CC is between 78% and 85% of V CC , the ISL6617
operates in interleaving mode with a fixed extension of
120ns and a variable extension of up to 70ns. This
results in a minimum extension of 120ns and a max of
190ns. To enter this 2nd interleaving mode, the pin must
remain in the 78% to 85% range for at least 4 cycles.
Between 54% and 64% of V CC , the device operates in
synchronous mode. Figures 4 and 5 show simplified
synchronous and interleaving modes’ operational
waveforms, respectively.
TABLE 1. ISL6617 OPERATIONAL MODES
To transition between two different modes, the
EN_PH_SYNC pin voltage level needs to be set
accordingly. Figures 6 and 7 show an example of external
circuits for mode transition between synchronous mode
and interleaving #1 or #2 mode, respectively. The R
should be less than 50k Ω to improve transition time.
PWM
PWMA
PWMB
FIGURE 4. INTERLEAVING MODE’S OPERATIONAL
WAVEFORMS (ENx = VCC, OR 81%*VCC)
PWM
MODE
Enable Low
MIN
TYP
MAX
0.8V
EXTENSION
PWMA
Enable High 2V
Interleaving#1 97%*VCC VCC 0ns to 70ns
Interleaving#2 78%*VCC 81%*VCC 85%*VCC 120ns + (0ns
to 70ns)
PWMB
FIGURE 5. SYNCHRONOUS MODE’S OPERATIONAL
WAVEFORMS (EN_PH_SYNC = 60%*VCC)
Synchronous
54%*VCC 60%*VCC 64%*VCC
0ns to 70ns
Not Used
From 0.8V to 2V or 54% of VCC is not
recommended Region.
40%*R
VCC
EN_PH_ SYNC
ISL6617
+
INTERLEAVING
0ns TO 70ns
60%*R
SYNC
-
+
4 CYCLES
BLANKING
INTERLEAVING
+120+(0ns TO 70ns)
-
-
+
+
SYNC
0ns TO 70ns
EN_PH
TTL
-
FIGURE 6. CONFIGURATION FOR TRANSITION BETWEEN SYNCHRONOUS AND INTERLEAVING #1 MODES
9
FN7564.0
February 4, 2010
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