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| 型号： | ISL78010ANZ-T |
| 厂商： | Intersil |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI-OUTP 32-TQFP |
| 标准包装： | 2,000 |
| 应用： | LCD 显示器，车用 |
| 电流 - 电源： | 1.7mA |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP（5x5） |
| 包装： | 带卷 (TR) |
ISL78010
I AVDD ( load ) > D × ( 1 – D ) × V IN
L = 10 μ H and I AVDD > 61mA
Equation 17 gives the boundary between discontinuous and
continuous boost operation. Continuous operation (LX
switching every clock cycle) requires:
--------------------------------------------------------------------------------------- (EQ. 17)
2 × L × f OSC
where the duty cycle, D = (A VDD - V IN )/A VDD
For example, with V IN = 5V, f OSC = 1.0MHz and
A VDD = 12V, continuous operation of the boost converter
can be guaranteed as shown in Equations 18, 19, and 20:
(EQ. 18)
output until the boost is enabled internally. The delayed
output appears at A VDD .
V BOOST soft-starts at the beginning of the third ramp. The
soft-start ramp depends on the value of the C DLY capacitor.
For C DLY of 220nF, the soft-start time is ~2ms.
V REF and V LOGIC turn on when input voltage (V DD )
exceeds 2.5V. When a fault is detected, the outputs and the
input protection will turn off but V REF will stay on.
V OFF turns on at the start of the fourth peak. At the fifth
peak, the open drain o/p DELB goes low to turn on the
external PMOS Q 4 to generate a delayed V BOOST output.
L = 6.8 μ H and I AVDD > 89mA
L = 3.3 μ H and I AVDD > 184mA
(EQ. 19)
(EQ. 20)
V ON is enabled at the beginning of the sixth ramp. A VDD ,
PG, V OFF , DELB and V ON are checked at end of this ramp.
Fault Protection
Charge Pump Output Capacitors
Ceramic capacitors with low ESR are recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
During the start-up sequence, prior to BOOST soft-start,
V REF is checked to be within ±20% of its final value, and the
device temperature is checked. If either of these is not within
the expected range, the part is disabled until the power is
recycled or EN is toggled.
C OUT ≥ ------------------------------------------------------
calculated as shown in Equation 21:
I OUT
2 × V RIPPLE × f OSC
(EQ. 21)
If C DELAY is shorted low, then the sequence will not start,
while if C DELAY is shorted H, the first down ramp will not
occur and the sequence will not complete.
where f OSC is the switching frequency.
Start-Up Sequence
Figure 28 shows a detailed start-up sequence waveform. For
a successful power-up, there should be six peaks at V CDLY .
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
When the input voltage is higher than 2.5V, an internal
current source starts to charge C CDLY to an upper threshold
using a fast ramp followed by a slow ramp. During the initial
slow ramp, the device checks whether there is a fault
condition. If no fault is found, C CDLY is discharged after the
first peak, and V REF turns on.
During the second ramp, the device checks the status of
V REF and over-temperature. At the peak of the second
ramp, PG output goes low and enables the input protection
PMOS Q 1 . Q 1 is a controlled FET used to prevent in-rush
current into V BOOST before V BOOST is enabled internally.
Its rate of turn-on is controlled by C o . When a fault is
detected, M1 will turn off and disconnect the inductor from
V IN .
the boost is not enabled, so V BOOST rises to V IN -V DIODE
through the output diode. Hence, there is a step at V BOOST
during this part of the start-up sequence. If this step is not
desirable, an external P-MOSFET can be used to delay the
15
Once the start-up sequence is completed, the chip
continuously monitors C DLY , DELB, FBP, FBL, FBN, V REF ,
FBB, and PG, and checks for faults. During this time, the
voltage on the C DLY capacitor remains at 1.15V until either a
fault is detected or the EN pin is pulled low.
A fault on C DELAY , V REF , or temperature will shut down the
chip immediately. If a fault on any other output is detected,
C DELAY will ramp up linearly with a 5μA (typical) current to
the upper fault threshold (typically 2.4V), at which point the
chip is disabled until the power is recycled or EN is toggled.
If the fault condition is removed prior to the end of the ramp,
the voltage on the C DLY capacitor returns to 1.15V.
Typical fault thresholds for FBP, FBL, FBN, and FBB are
included in the “Electrical Specifications” table beginning on
C INT has an internal current-limited clamp to keep the
voltage within its normal range. If C INT is shorted low, the
boost regulator will attempt to regulate to 0V. If C INT is
shorted H, the regulator switches to P mode.
If any of the regulated outputs (V BOOST , V ON , V OFF or
V LOGIC ) are driven above their target levels, the drive
circuitry will switch off until the output returns to its expected
value.
FN6501.2
December 4, 2013
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