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参数资料
| 型号： | ISL78010ANZ-T |
| 厂商： | Intersil |
| 文件页数： | 4/19页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI-OUTP 32-TQFP |
| 标准包装： | 2,000 |
| 应用： | LCD 显示器，车用 |
| 电流 - 电源： | 1.7mA |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP（5x5） |
| 包装： | 带卷 (TR) |
ISL78010
Electrical Specifications
V DD = 5V, V BOOST = 11V, I LOAD = 200mA, V ON = 15V, V OFF = -5V, V LOGIC = 2.5V, limits over -40°C to
+105°C temperature range, unless otherwise specified. Boldface limits apply over the operating
temperature range, -40°C to +105°C. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
CONDITION
(Note 6)
TYP
(Note 6)
UNIT
FAULT DETECTION
t FAULT
OT
I PG
Fault Time Out
Over-temperature Threshold
PG Pull-down Current
C DLY = 0.22μF
VPG > 0.6V
VPG < 0.6V
50
140
15
1.7
ms
°C
μA
mA
LOGIC ENABLE
V HI
V LO
Logic High Threshold
Logic Low Threshold
2.3
0.8
V
V
I LOW
Logic Low Bias Current
0.2
2
μA
I HIGH
Logic High Bias Current
at V EN = 5V
12
18
24
μA
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Pin Descriptions
PIN NAME
1, 2, 4, 6, 8, 10, 12,
16, 18, 23, 32
3
5
7
9
11
13
14, 27
15
17
19, 20, 21, 22
24
25
26
28
29
30
31
PIN NUMBER
NC
DELB
LX
DRVP
FBP
DRVL
FBL
SGND
DRVN
FBN
PGND
VREF
CINT
FBB
EN
VDD
PG
CDLY
4
DESCRIPTION
Not connected
Open drain output for gate drive of optional V BOOST delay FET
Drain of the internal N-Channel boost FET
Positive LDO base drive; open drain of an internal N-Channel FET
Positive LDO voltage feedback input pin; regulates to 1.2V nominal
Logic LDO base drive; open drain of an internal N-Channel FET
Logic LDO voltage feedback input pin; regulates to 1.2V nominal
Low noise signal ground
Negative LDO base drive; open drain of an internal P-Channel FET
Negative LDO voltage feedback input pin; regulates to 0.2V nominal
Power ground, connected to source of internal N-Channel boost FET
Bandgap reference output voltage; bypass with a 0.1μF to SGND
V BOOST integrator output; connect capacitor to SGND for PI-mode or connect to V DD for P-mode
operation
Boost regulator voltage feedback input pin; regulates to 1.2V nominal
Enable pin; High = Enable; Low or floating = Disable
Positive supply
Push-pull gate drive of optional fault protection FET; when chip is disabled or when a fault has been
detected, this is high
A capacitor connected from this pin to SGND sets the delay time for start-up sequence and sets the fault
timeout time
FN6501.2
December 4, 2013
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