参数资料
型号: ISL78200AVEZ
厂商: Intersil
文件页数: 15/22页
文件大小: 0K
描述: IC REG BUCK BOOST SYNC 20HTSSOP
标准包装: 740
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 可调至 0.8V
输入电压: 3 V ~ 40 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 2.2MHz
电流 - 输出: 2.5A
同步整流器: 两者兼有
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
包装: 管件
供应商设备封装: 20-HTSSOP
ISL78200
R1
EXT_BOOST
BATTERY
+
+
VOUT_BST
R2
0.8V
I_HYS = 3μA
R3
R4
AUXVCC
0.8V
LOGIC
PWM
LGATE
DRIVE
LGATE
I_HYS = 3μA
FIGURE 29. BOOST CONVERTER CONTROL
Referring to Figure 29, a resistor divider from boost input voltage
to the EXT_BOOST pin is used to detect the boost input voltage.
When the voltage on the EXT_BOOST pin is below 0.8V, the boost
Assuming VBAT is the boost input voltage, V OUTBST is the boost
output voltage and V OUT is the buck output voltage, the steady
state transfer functions are:
V OUTBST = ------------- ? VBAT
V OUT = D ? V OUTBST = ------------- ? VBAT
PWM is enabled with a fixed 500μs soft-start when the boost
duty cycle increases from t MINON *Fs to ~50% and a 3μA sinking
current is enabled at the EXT_BOOST pin for hysteresis purposes.
When the voltage on the EXT_BOOST pin recovers to above 0.8V,
the boost PWM is disabled immediately. Use Equation 3 to
1
1 – D
D
1 – D
(EQ. 5)
(EQ. 6)
calculate the upper resistor R UP (R1 in Figure 29) for a desired
hysteresis VHYS at boost input voltage
From Equation 5 and Equation 6, Equation 7 can be derived to
estimate the steady state boost output voltage as a function of
R UP [ M Ω ] = ----------------
VHYS
3 [ μ A ]
(EQ. 3)
VBAT and VOUT:
V OUTBST = VBAT + VOUT
(EQ. 7)
R LOW = ----------------------------
Use Equation 4 to calculate the lower resistor R LOW (R2 in
Figure 29) according to a desired boost enable threshold.
R UP ? 0.8
VFTH – 0.8
(EQ. 4)
After the IC starts up, the boost buck converters can keep
working when the battery voltage drops extremely low because
the IC’s bias (VCC) LDO is powered by the boost output. For an
example of 3.3V output application, when the battery drops to
2V, the VIN pin voltage is powered by the boost output voltage
P OUT
IL IN = -----------------------------
where VFTH is the desired falling threshold on boost input
voltage to turn on the boost, 3μA is the hysteresis current, and
0.8V is the reference voltage to be compared.
Note the boost start-up threshold has to be selected in a way that
the buck is operating well at close loop before boost start-up.
Otherwise, large inrush current at boost start-up could occur at
boost input due to the buck loop saturation.
Similarly, a resistor divider from boost output voltage to the
AUXVCC pin is used to detect the boost output voltage. When the
voltage on AUXVCC pin is below 0.8V, the boost PWM is enabled
with a fixed 500μs soft-start, and a 3μA sinking current is
enabled at AUXVCC pin for hysteresis purpose. When the voltage
on the AUXVCC pin recovers to above 0.8V, the boost PWM is
disabled immediately. Use Equation 3 to calculate the upper
resistor R UP (R3 in Figure 29) according to a desired hysteresis
VHY at boost output voltage. Use Equation 4 to calculate the
lower resistor R LOW (R4 in Figure 29) according to a desired
boost enable threshold at boost output.
15
that is 5.2V (Equation 7), meaning the VIN pin (buck input) still
needs 5.2V to keep the IC working.
Note in the above mentioned case, the boost input current could
be high because the input voltage is very low
(V IN *I IN = V OUT * I OUT / Efficiency). If the design is to achieve the
low input operation with full load, the inductor and MOSFET have
to be selected to have enough current ratings to handle the high
current appearing at boost input. The boost inductor current are
the same with the boost input current, which can be estimated in
Equation 8, where P OUT is the output power, VBAT is the boost
input voltage, and EFF is the estimated efficiency of the whole
boost and buck stages.
(EQ. 8)
VBAT ? EFF
Based on the same concerns of boost input current, the start-up
sequence must follow the rule that the IC is enabled after the
boost input voltage rise above a certain level. The shutdown
sequence must follow the rule that the IC is disabled first before
FN7641.2
December 24, 2013
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