参数资料
型号: ISL78200AVEZ
厂商: Intersil
文件页数: 20/22页
文件大小: 0K
描述: IC REG BUCK BOOST SYNC 20HTSSOP
标准包装: 740
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 可调至 0.8V
输入电压: 3 V ~ 40 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 2.2MHz
电流 - 输出: 2.5A
同步整流器: 两者兼有
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
包装: 管件
供应商设备封装: 20-HTSSOP
ISL78200
it is under the acceptable range. Suggest to run the iSim model
simulation to select the proper inductor value.
Boost Output Capacitor
Based on the same theory in boost start-up described above in
boost inductor selection, a large capacitor at boost output will
cause high inrush current at boost PWM start-up. 22μF is a good
choice for applications with buck output voltage less than 10V.
Also, some minimum amount of capacitance has to be used in
boost output to keep the system stable. Suggest to run the iSim
model simulation to select the proper inductor value.
Layout Suggestions
1. Put the input ceramic capacitors as close to the IC VIN pin and
power ground connecting to the power MOSFET or diode.
Keep this loop (input ceramic capacitor, IC V IN pin and
MOSFET/diode) as tiny as possible to achieve the least
voltage spikes induced by the trace parasitic inductance.
2. Put the input aluminum capacitors close to IC VIN pin.
3. Keep the phase node copper area small but large enough to
handle the load current.
4. Put the output ceramic and aluminum capacitors also close
to the power stage components.
5. Put vias (20 recommended) in the bottom pad of the IC. The
bottom pad should be placed in the ground copper plane with
an area as large as possible in multiple layers to effectively
reduce the thermal impedance.
6. Place the 4.7μF ceramic decoupling capacitor at the VCC pin
and as close as possible to the IC. Put multiple vias ( ≥ 3) close
to the ground pad of this capacitor.
7. Keep the bootstrap capacitor close to the IC.
8. Keep the LGATE drive trace as short as possible and try to
avoid using a via in the LGATE drive path to achieve the lowest
impedance.
9. Place the positive voltage sense trace close to the load for
tighter regulation.
10. Place all the peripheral control components close to the IC.
.
FIGURE 35. PCB VIA PATTERN
20
FN7641.2
December 24, 2013
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