参数资料
型号: ISL78200AVEZ
厂商: Intersil
文件页数: 18/22页
文件大小: 0K
描述: IC REG BUCK BOOST SYNC 20HTSSOP
标准包装: 740
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 可调至 0.8V
输入电压: 3 V ~ 40 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 2.2MHz
电流 - 输出: 2.5A
同步整流器: 两者兼有
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
包装: 管件
供应商设备封装: 20-HTSSOP
ISL78200
1 + ------
F 2 ( S ) = --- ? - = ----------------------- --------------------------------------
R o + R LP
d
S
S
ω o Q p
------- + -------------- + 1
ω o
+
^
i in
^
V in
IL d ^
1:D
V in d ^
^
i L
L P
RT
R LP
Rc
Co
^
v o
Ro
S
I
? o V in ω z
2
2
Current loop gain T i (S) is expressed as Equation 21:
T i ( S ) = R t F m F 2 ( S ) H e ( S )
(EQ. 20)
(EQ. 21)
d ^
T i(S)
The voltage loop gain with open current loop is Equation 22:
Fm
T v ( S ) = KF m F 1 ( S ) A v ( S )
(EQ. 22)
+
He(S)
Tv (S)
The Voltage loop gain with current loop closed is given by
Equation 23:
T v ( S )
1 + T i ( S )
v ^ comp
-Av(S)
FIGURE 32. SMALL SIGNAL MODEL OF BUCK REGULATOR
L v ( S ) = -----------------------
(EQ. 23)
If T i (S)>>1, then Equation 23 can be simplified as Equation 24:
F m = ---------------- = ------------------------------
1 + ------------
L v ( S ) = ----------------------- ---------------------- --------------- , ω p ≈ -------------
R o + R LP ω esr A v ( S ) 1
S H e ( S )
PWM Comparator Gain F m :
The PWM comparator gain Fm for peak current mode control is
given by Equation 16:
?
d 1 (EQ. 16)
?
v comp ( S e + S n ) T s
Where, S e is the slew rate of the slope compensation and S n is
given by Equation 17
S
(EQ. 24)
R t 1 + ------- R o C o
ω p
Equation 24 shows that the system is a single order system.
Therefore, a simple type II compensator can be easily used to
stabilize the system. While type III compensator is needed to
expand the bandwidth for current mode control in some cases.
L
V in – V o
S n = R t --------------------
P
(EQ. 17)
where, R t is the gain of the current amplifier.
R2
C1
R3
C3
CURRENT SAMPLING TRANSFER FUNCTION H E (S):
In current loop, the current signal is sampled every switching
cycle. It has the following transfer function in Equation 18:
V COMP
V REF
R BIAS
R1
V O
S
S
H e ( S ) = ------- + + 1
ω n Q n
2
2
ω n
--------------
(EQ. 18)
Q n = – --- , ω n = π f s
where, Q n and ω n are given by
2
π
FIGURE 33. TYPE III COMPENSATOR
A compensator with 2 zeros and 1 pole is recommended for this
1 + ------------
F 1 ( S ) = ------ = V in --------------------------------------
d ?
S
S
ω o Q p
------- + -------------- + 1
ω o
? 1 + ------------ ? ? 1 + ------------ ?
ω cz1 ? ?
ω cz2 ?
v ? comp
?
A v ( S ) = ---------------- = ------------------ ---------------------------------------------------------
SR 1 C
v ? O
? 1 + ---------- ?
S
?
ω ?
Power Stage Transfer Functions
Transfer function F 1 (S) from control to output voltage is:
S
?
v o ω esr
2
2
(EQ. 19)
part as shown in Figure 33. Its transfer function is expressed as
Equation 25:
S S
1 (EQ. 25)
1
cp
where ,
1
1
ω esr = ------------- , Q p ≈ R o ----- o - , ω o = -----------------
ω cz1 = -------------- , ω cz2 = -------------------------------- , ω cp = --------------
Loop bandwidth f c : ? -- 4 - to ------- ? f s
where ω z = ------------- .
Where,
C
R c C o L P L P C o
Transfer function F 2 (S) from control to inductor current is given
by Equation 20:
1
R o C o
18
1 1 1
R 2 C 1 ( R 1 + R 3 ) C 3 R 3 C 3
Compensator design goal:
? 1 1 ?
10
Gain margin: >10dB
FN7641.2
December 24, 2013
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