参数资料
| 型号： | ISL78211ARZ |
| 厂商： | Intersil |
| 文件页数： | 17/35页 |
| 文件大小： | 0K |
| 描述： | IC REG 1PHASE BUCK 40QFN |
| 标准包装： | 50 |
| 应用： | 转换器，Intel IMVP-6 |
| 输入电压： | 5 V ~ 21 V |
| 输出数： | 1 |
| 输出电压： | 0.3 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
ISL78211
10μA
OCSET
R OCSET
OC
INTERNAL TO ISL6261A
DROOP
VSUM
DFB
I PHASE
Rs
L
DCR
V O
C O
ESR
DROOP
1
VO
VSEN
1000pF
0~10
VCC-SENSE
TO PROCESSOR
1
RTN
1000pF
VSS-SENSE
SOCKET KELVIN
CONNECTIONS
330pF
VDIFF
FIGURE 6. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH CPU-DIE VOLTAGE SENSING AND INDUCTOR DCR CURRENT SENSING
C SOFT =
C SOFT = 200 μ A ( 10 mV μ s ) = 20 nF
= 2 . 8 mV
dV soft I ss 41 μ A
= =
dt
C SOFT
0 . 015 μ F
The IMVP-6? specification reveals the critical timing associated
with regulating the output voltage. SLEWRATE, given in the IMVP-
6? specification, determines the choice of the SOFT capacitor,
C SOFT , through Equation 2:
I GV (EQ. 2)
SLEWRATE
If SLEWRATE is 10mV/μs, and I GV is typically 200μA, C SOFT is
calculated as:
(EQ. 3)
Choosing 0.015 μ F will guarantee 10mV/μs SLEWRATE at
minimum I GV value. This choice of C SOFT controls the start-up
slew rate as well. One should expect the output voltage to slew to
the Boot value of 1.2V at a rate given by Equation 4:
(EQ. 4)
μ s
Selecting Rbias
To properly bias the ISL78211, a reference current needs to be
derived by connecting a 147k, 1% tolerance resistor from the RBIAS
pin to ground. This provides a very accurate 10μA current source
from which OCSET reference current is derived.
Caution should be used during layout. This resistor should be
placed in close proximity to the RBIAS pin and be connected to
good quality signal ground. Do not connect any other
components to this pin, as they will negatively impact the
performance. Capacitance on this pin may create instabilities
and should be avoided.
17
Start-up Operation - CLK_EN# and PGOOD
The ISL78211 provides a 3.3V logic output pin for CLK_EN#. The
system 3.3V voltage source connects to the 3V3 pin, which
powers internal circuitry that is solely devoted to the CLK_EN#
function. The output is a CMOS signal with 4mA sourcing and
sinking capability. CMOS logic eliminates the need for an
external pull-up resistor on this pin, eliminating the loss on the
pull-up resistor caused by CLK_EN# being low in normal
operation. This prolongs battery run time. The 3.3V supply should
be decoupled to digital ground, not to analog ground, for noise
immunity.
At start-up, CLK_EN# remains high until 13 clock cycles after the
core voltage is within 20mV of the boot voltage. The ISL78211
triggers an internal timer for the IMVP6_PWRGD signal (PGOOD
pin). This timer allows PGOOD to go high approximately 7ms
after CLK_EN# goes low.
Static Mode of Operation - Processor Die
Sensing
Remote sensing enables the ISL78211 to regulate the core
voltage at a remote sensing point, which compensates for
various resistive voltage drops in the power delivery path.
The VSEN and RTN pins of the ISL78211 are connected to Kelvin
sense leads at the die of the processor through the processor
socket. (The signal names are V CC_SENSE and V SS_SENSE
respectively). Processor die sensing allows the voltage regulator
to tightly control the processor voltage at the die, free of the
inconsistencies and the voltage drops due to layouts. The Kelvin
sense technique provides for extremely tight load line regulation
at the processor die side.
FN7578.1
December 4, 2013
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