参数资料
| 型号： | ISL78211ARZ |
| 厂商： | Intersil |
| 文件页数： | 4/35页 |
| 文件大小： | 0K |
| 描述： | IC REG 1PHASE BUCK 40QFN |
| 标准包装： | 50 |
| 应用： | 转换器，Intel IMVP-6 |
| 输入电压： | 5 V ~ 21 V |
| 输出数： | 1 |
| 输出电压： | 0.3 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 管件 |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
ISL78211
Functional Pin Descriptions
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28, 29, 30,
31, 32, 33,
34
35
36
37
38
39
40
SYMBOL
FDE
PMON
RBIAS
VR_TT#
NTC
SOFT
OCSET
VW
COMP
FB
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
VSS
VDD
NC
BOOT
UGATE
PHASE
VSSP
LGATE
VCCP
VID0, VID1, VID2, VID3,
VID4, VID5, VID6
VR_ON
DPRSLPVR
DPRSTP#
CLK_EN
3V3
PGOOD
4
DESCRIPTION
Forced diode emulation enable signal. Logic high of FDE with logic low of DPRSTP# forces the ISL78211 to
operate in diode emulation mode with an increased VW-COMP voltage window.
Analog voltage output pin. The voltage potential on this pin indicates the power delivered to the output.
A 147k Ω resistor to VSS sets internal current reference.
Thermal overload output indicator with open-drain output. Over-temperature pull-down resistance is 10.
Thermistor input to VR_TT# circuit and a 60μA current source is connected internally to this pin.
A capacitor from this pin to GND pin sets the maximum slew rate of the output voltage. The SOFT pin is the
non-inverting input of the error amplifier.
Overcurrent set input. A resistor from this pin to VO sets DROOP voltage limit for OC trip. A 10μA current source
is connected internally to this pin.
A resistor from this pin to COMP programs the switching frequency (eg. 6.81k = 300kHz).
The output of the error amplifier.
The inverting input of the error amplifier.
The output of the differential amplifier.
Remote core voltage sense input.
Remote core voltage sense return.
The output of the droop amplifier. DROOP-VO voltage is the droop voltage.
The inverting input of the droop amplifier.
An input to the IC that reports the local output voltage.
This pin is connected to one terminal of the capacitor in the current sensing R-C network.
Power stage input voltage. It is used for input voltage feed-forward to improve the input line transient
performance.
Signal ground. Connect to controller local ground.
5V control power supply.
Not connected. Ground this pin in the practical layout.
Upper gate driver supply voltage. An internal bootstrap diode is connected to the VCCP pin.
The upper-side MOSFET gate signal.
The phase node. This pin should connect to the source of upper MOSFET.
The return path of the lower gate driver.
The lower-side MOSFET gate signal.
5V power supply for the gate driver.
VID input with VID0 as the least significant bit (LSB) and VID6 as the most significant bit (MSB).
VR enable pin. A logic high signal on this pin enables the regulator.
Deeper sleep enable signal. A logic high indicates that the microprocessor is in Deeper Sleep Mode and also
indicates a slow Vo slew rate with 41mA discharging or charging the SOFT capacitor.
Deeper sleep slow wake up signal. A logic low signal on this pin indicates that the microprocessor is in Deeper
Sleep Mode.
Digital output for system PLL clock. Goes active 13 clock cycles after V CORE is within 20mV of the boot voltage.
3.3V supply voltage for CLK_EN#.
Power-good open-drain output. Needs to be pulled up externally by a 680 Ω resistor to VCCP or 1.9k to 3.3V.
FN7578.1
December 4, 2013
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| ISL78213ARZ | 功能描述:IC REG BUCK SYNC ADJ 3A 16VQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:降压（降压） 输出类型:两者兼有 输出数:1 输出电压:5V，1 V ~ 10 V 输入电压:3.5 V ~ 28 V PWM 型:电流模式 频率 - 开关:220kHz ~ 1MHz 电流 - 输出:600mA 同步整流器:无 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:16-SSOP（0.154"，3.90mm 宽） 包装:带卷 (TR) 供应商设备封装:16-QSOP |
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