参数资料
| 型号： | ISL78211ARZ |
| 厂商： | Intersil |
| 文件页数： | 21/35页 |
| 文件大小： | 0K |
| 描述： | IC REG 1PHASE BUCK 40QFN |
| 标准包装： | 50 |
| 应用： | 转换器，Intel IMVP-6 |
| 输入电压： | 5 V ~ 21 V |
| 输出数： | 1 |
| 输出电压： | 0.3 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 管件 |
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ISL78211
The effectiveness of the R n network is sensitive to the coupling
coefficient between the NTC thermistor and the inductor. The NTC
thermistor should be placed in close proximity of the inductor.
To verify whether the NTC network successfully compensates the
i core
Δ I core
V core Δ V core
DCR change over temperature, one can apply full load current,
wait for the thermal steady state, and see how much the output
voltage deviates from the initial voltage reading. Good thermal
compensation can limit the drift to less than 2mV. If the output
voltage decreases when the temperature increases, that ratio
between the NTC thermistor value and the rest of the resistor
divider network has to be increased. Following the evaluation
board value and layout of NTC placement will minimize the
engineering time.
The current sensing traces should be routed directly to the
inductor pads for accurate DCR voltage drop measurement.
V core
Δ V core = Δ I core × R droop
FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
i core
However, due to layout imperfection, the calculated R drp2 may
still need slight adjustment to achieve optimum load line slope. It
V core
V core
is recommended to adjust R drp2 after the system has achieved
thermal equilibrium at full load. For example, if the max current
is 20A, one should apply 20A load current and look for 42mV
output voltage droop. If the voltage droop is 40mV, the new value
FIGURE 11. LOAD TRANSIENT RESPONSE WHEN C n IS TOO SMALL
=
( R drp 1 + R drp 2 ) ? R drp 1
R drp 2 _ new
of R dpr2 is calculated by Equation 27:
42 mV
40 mV
(EQ. 27)
i core
For the best accuracy, the effective resistance on the DFB and
V core
V core
VSUM pins should be identical so that the bias current of the
droop amplifier does not cause an offset voltage. The effective
resistance on the VSUM pin is the parallel of R s and R n , and the
effective resistance on the DFB pin is the parallel of R drp1 and
R drp2 .
Dynamic Mode of Operation – Droop
Capacitor Design in DCR Sensing
Figure 10 shows the desired waveforms during load transient
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN C n IS TOO LARGE
The current sensing network consists of R n , R s and C n . The
effective resistance is the parallel of R n and R s . The RC time
constant of the current sensing network needs to match the
L/DCR time constant of the inductor to get correct
representation of the inductor current waveform as shown in
Equation 28:
? × C n
= ? ? n
response. V core needs to be as square as possible at I core change.
The V core response is determined by several factors, namely the
choice of output inductor and output capacitor, the compensator
design, and the droop capacitor design.
L
DCR
? R × R s ?
?
? R n + R s ?
(EQ. 28)
C n = DCR
The droop capacitor refers to C n in Figure 9. If C n is designed
correctly, its voltage will be a high-bandwidth analog voltage of
the inductor current. If C n is not designed correctly, its voltage will
be distorted from the actual waveform of the inductor current
and worsen the transient response. Figure 11 shows the
transient response when C n is too small. V core may sag
excessively upon load application to create a system failure.
Solving for Cn yields Equation 29:
L
R n × R s
R n + R s
(EQ. 29)
Figure 12 shows the transient response when C n is too large.
V core is sluggish in drooping to its final value. There will be
excessive overshoot if a load occurs during this time, which may
potentially hurt the CPU reliability.
For example: L = 0.45μH, DCR = 1.1m Ω , R s = 7.68k Ω , and
R n = 3.4k Ω
0.45 μ H
C n =
0 . 0011
parallel ( 7 . 68 k , 3 . 4 k )
= 174 nF
(EQ. 30)
Since the inductance and the DCR typically have 20% and 7%
tolerance respectively, the L/DCR time constant of each
individual inductor may not perfectly match the RC time constant
of the current sensing network. In mass production, this effect
will make the transient response vary a little bit from board-to-
21
FN7578.1
December 4, 2013
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| ISL78213ARZ | 功能描述:IC REG BUCK SYNC ADJ 3A 16VQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:降压（降压） 输出类型:两者兼有 输出数:1 输出电压:5V，1 V ~ 10 V 输入电压:3.5 V ~ 28 V PWM 型:电流模式 频率 - 开关:220kHz ~ 1MHz 电流 - 输出:600mA 同步整流器:无 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:16-SSOP（0.154"，3.90mm 宽） 包装:带卷 (TR) 供应商设备封装:16-QSOP |
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