参数资料
型号: ISL8102IRZ-T
厂商: Intersil
文件页数: 13/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 6,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 66.6%
电源电压: 4.75 V ~ 12.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL8102
If the R-C network components are selected such that the
R-C time constant matches the inductor L/DCR time
Once the desired output offset voltage has been determined,
use the following formulas to set R OFS :
R OFS = --------------------------
constant, then V DROOP is equal to the sum of the voltage
drops across the individual DCRs, multiplied by a gain. As
Equation 8 shows, V DROOP is therefore proportional to the
total output current, I OUT .
For Positive Offset (connect R OFS to GND):
0.5 ? R 1
V OFFSET
(EQ. 9)
V DROOP = --------------------- ? I OUT ? DCR
R OFS = --------------------------
R COMP
R S
L
V L (s)
DCR
(EQ. 8)
I OUT
For Negative Offset (connect R OFS to VCC):
1.5 ? R 1
V OFFSET
(EQ. 10)
PHASE 1
INDUCTOR
V OUT
VDIFF
L 1
L 2
PHASE 2
R S
R S
I
I
L
DCR
INDUCTOR
C OUT
+
V OFS
-
R 1
FB
I OFS
VREF
E/A
ISUM
ICOMP
C COMP
R COMP
-
DROOP
V DROOP
+ IREF
C SUM
(Optional)
R OFS
OFS
ISL8102
+
-
0.5V
-
+
1.5V
ISL8102
GND
GND
VCC
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
FIGURE 7. DCR SENSING CONFIGURATION
By simply adjusting the value of R S , the load line can be set
to any level, giving the converter the right amount of droop at
VDIFF
PROGRAMMING
all load currents. It may also be necessary to compensate for
any changes in DCR due to temperature. These changes
cause the load line to be skewed, and cause the R-C time
-
V OFS
+
R 1
VREF
constant to not match the L/DCR time constant. If this
becomes a problem a simple negative temperature
coefficient resistor network can be used in the place of
R COMP to compensate for the rise in DCR due to
temperature.
Output Voltage Offset Programming
The ISL8102 allows the designer to accurately adjust the
I OFS
V CC
FB
E/A
offset voltage by connecting a resistor, R OFS , from the OFS
pin to VCC or GND. When R OFS is connected between OFS
and VCC, the voltage across it is regulated to 1.5V. This
R OFS
+
-
+
1.5V
causes a proportional current (I OFS ) to flow into the OFS pin
and out of the FB pin. If R OFS is connected to ground, the
voltage across it is regulated to 0.5V, and I OFS flows into the
OFS
ISL8102
-
GND
0.5V
VCC
FB pin and out of the OFS pin. The offset current flowing
through the resistor between VDIFF and FB will generate the
desired offset voltage which is equal to the product (I OFS x
R 1 ). These functions are shown in Figures 8 and 9.
13
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
FN9247.1
July 28, 2008
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