参数资料
型号: ISL8102IRZ-T
厂商: Intersil
文件页数: 22/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 6,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 66.6%
电源电压: 4.75 V ~ 12.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL8102
G MOD ( f ) = ------------------------------ ? -----------------------------------------------------------------------------------------------------------
V OSC
1 + s ( f ) ? ( ESR + DCR ) ? C + s ( f ) ? L ? C
C 2
d MAX ? V IN 1 + s ( f ) ? ESR ? C
2
G FB ( f ) = ---------------------------------------------------- ?
1 + s ( f ) ? ( R 1 + R 3 ) ? C 3
( 1 + s ( f ) ? R 3 ? C 3 ) ? ? 1 + s ( f ) ? R 2 ? ? ? ?
? ? C 1 ? C 2 ? ?
COMP
R 2
E/A
C 1
-
+
VREF
FB
R 3
R 1
C 3
1 + s ( f ) ? R 2 ? C 1
s ( f ) ? R 1 ? ( C 1 + C 2 )
(EQ. 34)
-------------------------------------------------------------------------------------------------------------------------
---------------------
? ? C 1 + C 2 ? ?
VDIFF
G CL ( f ) = G MOD ( f ) ? G FB ( f )
where , s ( f ) = 2 π ? f ? j
-
+
RGND
VSEN
2. Calculate C 1 such that F Z1 is placed at a fraction of the F LC ,
at 0.1 to 0.75 of F LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F CE /F LC , the lower the F Z1
C 1 = -----------------------------------------------
PWM
CIRCUIT
OSCILLATOR
V OSC
V IN
V OUT
frequency (to maximize phase boost at F LC ).
1
2 π ? R 2 ? 0.5 ? F LC
3. Calculate C 2 such that F P1 is placed at F CE .
(EQ. 31)
2 π ? R 2 ? C 1 ? F CE – 1
HALF-BRIDGE
UGATE
L
DCR
C 1
C 2 = --------------------------------------------------------
(EQ. 32)
DRIVE
PHASE
C
4. Calculate R 3 such that F Z2 is placed at F LC . Calculate C 3
such that F P2 is placed below F SW (typically, 0.5 to 1.0
LGATE
ESR
times F SW ). F SW represents the per-channel switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F P2 lower in frequency
ISL8102
EXTERNAL CIRCUIT
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
R 3 = ----------------------
F SW
------------ – 1
F LC
C 3 = -------------------------------------------------
FIGURE 22. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The compensation network consists of the error amplifier
(internal to the ISL8102) and the external R 1 -R 3 , C 1 -C 3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F 0 ; typically 0.1 to 0.3 of F SW ) and adequate
phase margin (better than 45°). Phase margin is the
difference between the closed loop phase at F 0dB and +180°.
Equations 29 to 35 relate the compensation network’s poles,
zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 , and
C 3 ) in Figures 20 and 21. Use the following guidelines for
locating the poles and zeros of the compensation network:
1. Select a value for R 1 (1k Ω to 5k Ω , typically). Calculate
COMP pin and minimizing resultant duty cycle jitter.
R 1
(EQ. 33)
1
2 π ? R 3 ? 0.7 ? F SW
It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier ’s open-loop gain. Verify phase margin results and
adjust as necessary. Equation 34 describe the frequency
response of the modulator (G MOD ), feedback compensation
(G FB ) and closed-loop response (G CL )
:
COMPENSATION BREAK FREQUENCY EQUATIONS
F Z1 = -------------------------------
F Z2 = -------------------------------------------------
F P1 = ---------------------------------------------
2 π ? R 2 ? ---------------------
F P2 = -------------------------------
value for R 2 for desired converter bandwidth (F 0 ). If
setting the output voltage to be equal to the reference set
voltage as shown in Figure 22, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 6), in order
1
2 π ? R 2 ? C 1
1
2 π ? ( R 1 + R 3 ) ? C 3
1
C 1 ? C 2
C 1 + C 2
1
2 π ? R 3 ? C 3
(EQ. 35)
to compensate for the attenuation introduced by the
resistor divider, the obtained R 2 value needs be
multiplied by a factor of (R P1 + R S1 )/R P1 . The remainder
of the calculations remain unchanged, as long as the
compensated R 2 value is used.
Figure 23 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
d MAX ? V IN ? F LC
V OSC ? R 1 ? F 0
R 2 = ---------------------------------------------
22
(EQ. 30)
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
FN9247.1
July 28, 2008
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