参数资料
型号: ISL8102IRZ-T
厂商: Intersil
文件页数: 20/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 6,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 66.6%
电源电压: 4.75 V ~ 12.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL8102
L
V L (s)
DCR
I OUT
PHASE1
R S
I
INDUCTOR
L 1
V OUT
C OUT
Δ V 1
Δ V 2
L
DCR
V OUT
PHASE2
ISUM
R S
I
INDUCTOR
L 2
Δ I
I TRAN
ICOMP
C COMP
R COMP
FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR
-
DROOP
V DROOP
Compensation
The two opposing goals of compensating the voltage
ISL8102
IREF
+
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation (as
(DCR Current Sensing)” on page 19)” there are two distinct
methods for achieving these goals.
FIGURE 18. DCR SENSING CONFIGURATION
Due to errors in the inductance or DCR it may be necessary
to adjust the value of R COMP to match the time constants
correctly. The effects of time constant mismatch can be seen
in the form of droop overshoot or undershoot during the
initial load transient spike, as shown in Figure 19. Follow the
steps below to ensure the R-C and inductor L/DCR time
constants are matched accurately.
1. Capture a transient event with the oscilloscope set to
about L/DCR/2 (sec/div). For example, with L = 1μH and
DCR = 1m Ω , set the oscilloscope to 500μs/div.
Compensating the Load-Line Regulated Converter
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R 2 and C 1
.
C 2 (OPTIONAL)
2. Record Δ V 1 and Δ V 2 as shown in Figure 19.
3. Select a new value, R COMP,2 , for the time constant
R 2
C 1
COMP
resistor based on the original value, R COMP,1 , using
Equation 27.
FB
R COMP , 2 = R COMP , 1 ? ----------
Δ V 1
Δ V 2
(EQ. 27)
R 1
ISL8102
4. Replace R COMP with the new value and check to see that
the error is corrected. Repeat the procedure if necessary.
After choosing a new value for R COMP , it will most likely be
necessary to adjust the value of R S to obtain the desired full
load droop voltage. Use Equation 26 to obtain the new value
for R S .
20
VDIFF
FIGURE 20. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL8102 CIRCUIT
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
FN9247.1
July 28, 2008
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