参数资料
型号: ISL8103IRZ-T
厂商: Intersil
文件页数: 17/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 40-QFN
标准包装: 1
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 66.6%
电源电压: 4.75 V ~ 12.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 剪切带 (CT)
产品目录页面: 1244 (CN2011-ZH PDF)
其它名称: ISL8103IRZ-TCT
ISL8103
Undervoltage Detection
The undervoltage threshold is set at 82% of the REF
voltage. When the output voltage (VSEN-RGND) is below
the undervoltage threshold, PGOOD gets pulled low. No
other action is taken by the controller. PGOOD will return
high if the output voltage rises above 85% of the REF
voltage.
Overvoltage Protection
The ISL8103 constantly monitors the difference between the
VSEN and RGND voltages to detect if an overvoltage event
occurs. During soft-start, while the DAC/REF is ramping up,
the overvoltage trip level is the higher of REF plus 150mV or
a fixed voltage, V OVP . The fixed voltage, V OVP , is 1.67V.
Upon successful soft-start, the overvoltage trip level is only
REF plus 150mV. OVP releases 50mV below its trip point if it
was “REF plus 150mV” that tripped it, and releases 100mV
below its trip point if it was the fixed voltage, V OVP , that
tripped it. Actions are taken by the ISL8103 to protect the
If VSEN or RGND become opened, VDIFF falls, causing the
duty cycle to increase and the output voltage on IREF to
increase. If the voltage on IREF exceeds “VDIFF+1V”, the
controller will shut down. Once the voltage on IREF falls
below “VDIFF+1V”, the ISL8103 will restart at the beginning
of soft-start.
Overcurrent Protection
The ISL8103 detects overcurrent events by comparing the
droop voltage, V DROOP , to the OCSET voltage, V OCSET , as
shown in Figure 13. The droop voltage, set by the external
current sensing circuitry, is proportional to the output current
as shown in Equation 8. A constant 100μA flows through
R OCSET , creating the OCSET voltage. When the droop
voltage exceeds the OCSET voltage, the overcurrent
protection circuitry activates. Since the droop voltage is
proportional to the output current, the overcurrent trip level,
I MAX , can be set by selecting the proper value for R OCSET ,
as shown in Equation 13.
100 μ A ? R S
load when an overvoltage condition occurs, until the output
voltage falls back within set limits.
At the inception of an overvoltage event, all LGATE signals
I MAX ? R COMP ? DCR
R OCSET = ----------------------------------------------------------
(EQ. 13)
are commanded high, and the PGOOD signal is driven low.
This causes the controller to turn on the lower MOSFETs
and pull the output voltage below a level that might cause
damage to the load. The LGATE outputs remain high until
VDIFF falls to within the overvoltage limits explained above.
The ISL8103 will continue to protect the load in this fashion
as long as the overvoltage condition recurs.
Once an overvoltage condition ends the ISL8103 continues
normal operation and PGOOD returns high.
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL8103 is designed to protect the load from any overvoltage
events that may occur. This is accomplished by means of an
internal 10k Ω resistor tied from PHASE to LGATE, which
turns on the lower MOSFET to control the output voltage
until the overvoltage event ceases or the input power supply
cuts off. For complete protection, the low side MOSFET
should have a gate threshold well below the maximum
voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL8103 is designed to detect this
and shut down the controller. This event is detected by
monitoring the voltage on the IREF pin, which is a local
version of V OUT sensed at the outputs of the inductors.
17
Once the output current exceeds the overcurrent trip level,
V DROOP will exceed V OCSET , and a comparator will trigger
the converter to begin overcurrent protection procedures. At
the beginning of overcurrent shutdown, the controller turns
off both upper and lower MOSFETs. The system remains in
this state for a period of 4096 switching cycles. If the
controller is still enabled at the end of this wait period, it will
attempt a soft-start (as shown in Figure 14). If the fault
remains, the trip-retry cycles will continue indefinitely until
either the controller is disabled or the fault is cleared. Note
that the energy delivered during trip-retry cycling is much
less than during full-load operation, so there is no thermal
hazard.
OUTPUT CURRENT
0A
OUTPUT VOLTAGE
0V
FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE
FN9246.1
July 21, 2008
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