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| 型号： | ISL8103IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 23/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 1 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 66.6% |
| 电源电压： | 4.75 V ~ 12.6 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 剪切带 (CT) |
| 产品目录页面： | 1244 (CN2011-ZH PDF) |
| 其它名称： | ISL8103IRZ-TCT |
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ISL8103
2 π ? R 2 ? C 1 ? F CE – 1
3. Calculate C 2 such that F P1 is placed at F CE .
C 1
C 2 = --------------------------------------------------------
(EQ. 32)
F Z1 F Z2
F P1
F P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
4. Calculate R 3 such that F Z2 is placed at F LC . Calculate C 3
such that F P2 is placed below F SW (typically, 0.5 to 1.0
20 log ? -------- ?
OSC
times F SW ). F SW represents the per-channel switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F P2 lower in
frequency helps reduce the gain of the compensation
0
R2
? R1 ?
d MAX ? V IN
20 log ---------------------------------
V
G FB
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
G CL
G MOD
R 3 = ----------------------
F SW
FREQUENCY
F CE
F LC
F 0
R 1
------------ – 1
F LC
(EQ. 33)
LOG
FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
C 3 = -------------------------------------------------
G MOD ( f ) = ------------------------------ ? -----------------------------------------------------------------------------------------------------------
V OSC
1 + s ( f ) ? ( ESR + DCR ) ? C + s ( f ) ? L ? C
1 + s ( f ) ? R 2 ? C 1
s ( f ) ? R 1 ? ( C 1 + C 2 )
G FB ( f ) = ---------------------------------------------------- ?
1 + s ( f ) ? ( R 1 + R 3 ) ? C 3
( 1 + s ( f ) ? R 3 ? C 3 ) ? ? 1 + s ( f ) ? R 2 ? ? --------------------- ? ?
1
2 π ? R 3 ? 0.7 ? F SW
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier ’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G MOD ), feedback
compensation (G FB ) and closed-loop response (G CL ):
d MAX ? V IN 1 + s ( f ) ? ESR ? C
2
(EQ. 34)
? -------------------------------------------------------------------------------------------------------------------------
? ? C 1 ? C 2 ? ?
? ? C 1 + C 2 ? ?
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the per-channel switching frequency, F SW .
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
G CL ( f ) = G MOD ( f ) ? G FB ( f )
where , s ( f ) = 2 π ? f ? j
increases or decreases to meet the demand.
COMPENSATION BREAK FREQUENCY EQUATIONS
In high-speed converters, the output capacitor bank is
F Z1 = -------------------------------
F Z2 = -------------------------------------------------
F P1 = ---------------------------------------------
2 π ? R 2 ? ---------------------
(EQ. 35)
F P2 = -------------------------------
1
2 π ? R 2 ? C 1
1
2 π ? ( R 1 + R 3 ) ? C 3
1
C 1 ? C 2
C 1 + C 2
1
2 π ? R 3 ? C 3
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, Δ I, the load-current slew rate, di/dt, and the
maximum allowable output-voltage deviation under transient
Figure 22 shows an asymptotic plot of the DC/DC
converter ’s gain vs. frequency. The actual Modulator Gain
has a high gain peak dependent on the quality factor (Q) of
the output filter, which is not shown. Using the above
guidelines should yield a compensation gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F P2
against the capabilities of the error amplifier. The closed loop
gain, G CL , is constructed on the log-log graph of Figure 22
by adding the modulator gain, G MOD (in dB), to the feedback
compensation gain, G FB (in dB). This is equivalent to
multiplying the modulator transfer function and the
compensation transfer function and then plotting the
resulting gain.
23
loading, Δ V MAX . Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
FN9246.1
July 21, 2008
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