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参数资料
| 型号： | ISL8112EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 21/27页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL8112 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 0.7 ~ 5.5 V |
| 电流 - 输出： | 200mA |
| 输入电压： | 5.5 ~ 25 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 可调式 |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL8112 |
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ISL8112
Discharge Mode (Soft-Stop)
When a transition to standby or shutdown mode occurs, or
the output is discharged to GND through an internal 25 Ω
switch, the reference remains active to provide an accurate
threshold and to provide overvoltage protection.
When the output undervoltage fault latch is set, both
channels are discharged to GND through the internal 25 Ω
switches.
Shutdown Mode
The ISL8112 SMPS1, SMPS2 and LDO have independent
enabling control. Drive EN1, EN2 and EN_LDO below the
precise input falling-edge trip level to place the ISL8112 in its
low-power shutdown state. The ISL8112 consumes only
20μA of quiescent current while in shutdown. When
shutdown mode activates, the 3.3V VREF2 remain on. Both
SMPS outputs are discharged to 0V through a 25 Ω switch.
Power-Up Sequencing and On/Off Controls (EN_)
EN1 and EN2 control SMPS power-up sequencing. EN1 or
EN2 rising above 2.4V enables the respective outputs. EN1
or EN2 falling below 1.6V disables the respective outputs.
Connecting EN1 or EN2 to VREF1 will force its outputs off
while the other output is below regulation. The sequenced
SMPS will start once the other SMPS reaches regulation.
The second SMPS remains on until the first SMPS turns off,
the device shuts down, a fault occurs or PVCC goes into
undervoltage lockout. Both supplies begin their power-down
sequence immediately when the first supply turns off. Driving
EN_ below 0.8V clears the overvoltage, undervoltage and
thermal fault latches.
TABLE 3. OPERATING-MODE TRUTH TABLE
MODE
Power-Up
Run
Overvoltage
Protection
Undervoltage
Protection
Discharge
Standby
Shutdown
Thermal Shutdown
CONDITION
PVCC < UVLO threshold.
EN_LDO = high, EN1 or EN2
enabled.
Either output > 111% (VSEN1) or
116% (VSEN2) of nominal level.
Either output < 70% of nominal after
20ms time-out expires and output is
enabled.
Either SMPS output is still high in
either standby mode or shutdown
mode
EN1, EN2 < startup threshold,
EN_LDO= High
EN1, EN2, EN_LDO = low
TJ > +150°C
COMMENT
Transitions to discharge mode after a PVCC UVLO and after VREF1 becomes valid.
LDO, VREF2, and VREF1 remain active.
Normal operation
LG_ is forced high. LDO, VREF2 and VREF1 active. Exited by a PVCC UVLO, VCC
POR, or by toggling EN1 or EN2.
Both the internal 25 ? switches turn on. LDO, VREF2 and VREF1 are active. Exited
by a PVCC UVLO, or by toggling EN1 or EN2.
Discharge switch (25 Ω ) connects VSEN_ to GND. One output may still run while the
other is in discharge mode. Activates when PVCC is in UVLO, or transition to UVLO,
standby, or shutdown has begun. LDO, VREF2 and VREF1 active.
LDO, VREF2 and VREF1 active.
Discharge switch (25 Ω ) connects VSEN_ to PGND. All circuitry off except VREF2.
All circuitry off. Exited by PVCC UVLO or cycling EN_. VREF2 remain active.
TABLE 4. SHUTDOWN AND STANDBY CONTROL LOGIS
VEN_LDO
Low
“>2.5” → High
“>2.5” → High
“>2.5” → High
“>2.5” → High
“>2.5” → High
“>2.5” → High
VEN1 (V)
Low
Low
High
High
Low
High
VREF1
VEN2 (V)
Low
Low
High
Low
High
VREF1
High
LDO
Off
On
On
On
On
On
On
SMPS1
Off
Off
On
On
Off
On
On (after SMPS2 is up)
SMPS2
Off
Off
On
Off
On
On (after SMPS1 is up)
On
21
FN6396.1
August 10, 2010
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