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参数资料
| 型号： | ISL8112EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 7/27页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL8112 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 0.7 ~ 5.5 V |
| 电流 - 输出： | 200mA |
| 输入电压： | 5.5 ~ 25 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 可调式 |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL8112 |
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ISL8112
Pin Descriptions
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NAME
VREF1
FS
VCC
EN_LDO
VREF2
VIN
LDO
LDOREF
BYP
VSEN1
FB1
ILIM1
PGOOD1
EN1
UG1
PH1
BOOT1
LG1
PVCC
NC
GND
PGND
FUNCTION
2V Reference Output. Bypass to GND with a 0.1μF (min) capacitor. VREF1 can source up to 50 μ A for external loads.
Loading VREF1 degrades FB and output accuracy according to the VREF1 load-regulation error.
Frequency Select Input. Connect to GND for 400kHz/500kHz operation. Connect to VREF1 (or leave OPEN) for
400kHz/300kHz operation. Connect to VCC for 200kHz/300kHz operation (5V/3.3V SMPS switching frequencies,
respectively).
Analog Supply Voltage for PWM Core. Bypass to GND with a 1μF ceramic capacitor.
LDO Enable Input. The LDO is enabled if EN_LDO is within logic high level and VIN is higher than POR threshold. The
LDO is disabled if EN_LDO is less than the logic low level.
3.3V Reference Output. VREF2 can source up to 5mA for external loads. Bypass to GND with a 0.01μF capacitor if
loaded. Leave open if there is no load.
Power-Supply Input. VIN is used for the constant-on-time PWM on-time one-shot circuits. VIN is also used to power the
linear regulators. The linear regulators are powered by SMPS1 if VSEN1 is set greater than 4.78V and BYP is tied to
VSEN1. Connect VIN to the battery input and bypass with a 1μF capacitor.
Linear-Regulator Output. LDO can provide a total of 100mA external loads. The LDO regulate at 5V If LDOREF is
connected to GND. When the LDO is set at 5V and BYP is within 5V switch over threshold, the internal regulator shuts
down and the LDO output pin connects to BYP through a 0.7 Ω switch. The LDO regulate at 3.3V if LDOREF is
connected to VCC. When the LDO is set at 3.3V and BYP is within 3.3V switch over threshold, the internal regulator
shuts down and the LDO output pin connects to BYP through a 1.5 Ω switch. Bypass LDO output with a minimum of
4.7μF ceramic.
LDO Reference Input. Connect LDOREF to GND for fixed 5V operation. Connect LDOREF to VCC for fixed 3.3V
operation. LDOREF can be used to program LDO output voltage from 0.7V to 4.5V. LDO output is two times the voltage
of LDOREF. There is no switch over in adjustable mode.
BYP is the switch over source voltage for the LDO when LDOREF connected to GND or VCC. Connect BYP to 5V if
LDOREF is tied to GND. Connect BYP to 3.3V if LDOREF is tied to VCC. The BYP is also controlled by EN_LDO. When
LDOREFIN is tied to GND, the BYP is not switched over to LDO until SMPS1 finished soft-starting.
SMPS1 Output Voltage-Sense Input. Connect to the SMPS1 output. VSEN1 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS1 feedback input in fixed-voltage mode.
SMPS1 Feedback Input. Connect FB1 to GND for fixed 5V operation. Connect FB1 to VCC for fixed 1.5V operation
Connect FB1 to a resistive voltage-divider from VSEN1 to GND to adjust the output from 0.7V to 5.5V.
SMPS1 Current-Limit Adjustment. The GND-PH1 current-limit threshold is 1/10th the voltage seen at ILIM1 over a 0.2V
to 2V range. There is an internal 5μA current source from VCC to ILIM1. Connect ILIM1 to VREF1 for a fixed 200mV
threshold. The logic current limit threshold is default to 100mV value if ILIM1 is higher than VCC - 1V.
SMPS1 Power-Good Open-Drain Output. PGOOD1 is low when the SMPS1 output voltage is more than 10% below the
normal regulation point or during soft-start. PGOOD1 is high impedance when the output is in regulation and the soft-
start circuit has terminated. PGOOD1 is low in shutdown.
SMPS1 Enable Input. The SMPS1 is enabled if EN1 is greater than the logic high level and disabled if EN1 is less than
the logic low level. If EN1 is connected to VREF1, the SMPS1 starts after the SMPS2 reaches regulation (delay start).
Drive EN1 below 0.8V to clear fault level and reset the fault latches.
High-Side MOSFET Floating Gate-Driver Output for SMPS1. UG1 swings between PH1 and BOOT1.
Inductor Connection for SMPS1. PH1 is the internal lower supply rail for the UG1 high-side gate driver. PH1 is the
current-sense input for the SMPS1.
Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor according to the typical application
circuits (Figure 17 and Figure 18). See “MOSFET Gate Drivers (UG_, LG_)” on page 19.
SMPS1 Synchronous-Rectifier Gate-Drive Output. LG1 swings between GND and PVCC.
PVCC is the supply voltage for the low-side MOSFET driver LG_. Connect a 5V power source to the PVCC pin (bypass
with 1μF MLCC capacitor to PGND if necessary). There is internal 10 Ω PFET connecting PVCC to VCC. Make sure
that both VCC and PVCC are bypassed with 1μF MLCC capacitors.
No connection pin. Externally connect it to ground.
Analog Ground for both SMPS_ and LDO. Connect externally to the underside of the exposed pad.
Power Ground for SMPS_ controller. Connect PGND externally to the underside of the exposed pad.
7
FN6396.1
August 10, 2010
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| ISL8115EVAL1Z | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High Voltage Synchronous Buck PWM Controller with Integrated Gate Driver and Current Sharing Capability |
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