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参数资料
| 型号： | ISL8112EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 8/27页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL8112 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 0.7 ~ 5.5 V |
| 电流 - 输出： | 200mA |
| 输入电压： | 5.5 ~ 25 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 可调式 |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL8112 |
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ISL8112
Pin Descriptions (Continued)
PIN
23
24
25
26
27
28
29
30
31
NAME
LG2
BOOT2
PH2
UG2
EN2
PGOOD2
MODE
VSEN2
ILIM2
FUNCTION
SMPS2 Synchronous-Rectifier Gate-Drive Output. LG2 swings between GND and PVCC.
Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor according to the typical application
circuits (Figure 17 and Figure 18). See “MOSFET Gate Drivers (UG_, LG_)” on page 19 .
Inductor Connection for SMPS2. PH2 is the internal lower supply rail for the UG2 high-side gate driver. PH2 is the
current-sense input for the SMPS2.
High-Side MOSFET Floating Gate-Driver Output for SMPS2. UG1 swings between PH2 and BOOT2.
SMPS2 Enable Input. The SMPS2 is enabled if EN2 is greater than the logic high level and disabled if EN2 is less than
the logic low level. If EN2 is connected to VREF1, the SMPS2 starts after the SMPS1 reaches regulation (delay start).
Drive EN2 below 0.8V to clear fault level and reset the fault latches.
SMP2 Power-Good Open-Drain Output. PGOOD2 is low when the SMPS2 output voltage is more than 10% below the
normal regulation point or during soft-start. PGOOD2 is high impedance when the output is in regulation and the soft-
start circuit has terminated. PGOOD2 is low in shutdown.
Low-Noise Mode Control. Connect MODE to GND for normal Idle-Mode (pulse-skipping) operation or to VCC for PWM
mode (fixed frequency). Connect to VREF1 or leave floating for ultrasonic skip mode operation.
SMPS2 Output Voltage-Sense Input. Connect to the SMPS2 output. VSEN2 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS2 feedback input in fixed-voltage mode.
SMPS2 Current-Limit Adjustment. The GND-PH1 current-limit threshold is 1/10th the voltage seen at ILIM2 over a 0.2V
to 2V range. There is an internal 5μA current source from VCC to ILIM2. Connect ILIM2 to VREF1 for a fixed 200mV.
The logic current limit threshold is default to 100mV value if ILIM2 is higher than VCC - 1V.
32
OUT2REF Output voltage control for SMPS2. Connect OUT2REF to VCC for fixed 3.3V. Connect OUT2REF to VREF2 for fixed
1.05V. OUT2REF can be used to program SMPS2 output. VSEN2 equals OUT2REF from 0.5V to 2.50V. SMPS2 output
voltage is 0V if OUT2REF < 0.5V.
Typical Performance Curves
Circuit of Figure 17 and Figure 18, no load on LDO, VSEN1, VSEN2, VREF2, and VREF1,
V IN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN_LDO = 5V, T A = -40°C to +100°C,
unless otherwise noted. Typical values are at T A = +25°C.
1.0
7 V IN SKIP MODE
7 V IN PWM MODE
7 V IN ULTRA SKIP MODE
12 V IN SKIP MODE
12 V IN PWM MODE
12 V IN ULTRA SKIP MODE
25 V IN SKIP MODE
25 V IN PWM MODE
25 V IN ULTRA SKIP MODE
1.0
7 V IN SKIP MODE
7 V IN PWM MODE
7 V IN ULTRA SKIP MODE
12 V IN SKIP MODE
12 V IN PWM MODE
12 V IN ULTRA SKIP MODE
25 V IN SKIP MODE
25 V IN PWM MODE
25 V IN ULTRA SKIP MODE
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.001
0.010
0.100
1.000
10.000
0
0.001
0.010
0.100
1.000
10.000
OUTPUT LOAD (A)
FIGURE 1. V OUT2 = 1.05V EFFICIENCY vs LOAD (300kHz)
8
OUTPUT LOAD (A)
FIGURE 2. V OUT1 = 1.5V EFFICIENCY vs LOAD (200kHz)
FN6396.1
August 10, 2010
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