参数资料
型号: ISL8204MIRZ-T
厂商: Intersil
文件页数: 11/21页
文件大小: 0K
描述: IC BUCK SYNC ADJ 4A 15QFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 500
类型: 非隔离(POL)
输出数: 1
电压 - 输入(最小): 1V
电压 - 输入(最大): 20V
Voltage - Output 1: 0.6 ~ 6 V
电流 - 输出(最大): 4A
电源(瓦) - 制造商系列: 24W
安装类型: 表面贴装
封装/外壳: 15-BQFN
尺寸/尺寸: 0.59" L x 0.59" W x 0.14" H(15.0mm x 15.0mm x 3.5mm)
包装: 带卷 (TR)
工作温度: -40°C ~ 85°C
效率: 95%
电源(瓦特)- 最大: 24W
ISL8204M, ISL8206M
COMP/EN
From T 1 , there is a nominal 6.8ms delay, which allows the PVCC
pin to exceed 6.5V (if rising up towards 12V), so that the internal
bias regulator can turn on cleanly. At the same time, the ISET pin
is initialized by disabling the low-side gate driver and drawing I SET
(nominal 21.5μA) through R SETI . This sets up a voltage that will
represent the I SET trip point. At T 2 , there is a variable time period
for the OCP sample and hold operation (0.0ms to 3.4ms
nominal; the longer time occurs with the higher overcurrent
setting). The sample and hold operation uses a digital counter
and DAC to save the voltage, so the stored value does not
degrade, as long as the P VCC is above V PORR (see “Overcurrent
Protection (OCP)” on page 12 for more details on the equations
and variables). Upon the completion of sample and hold at T 3 ,
the soft-start operation is initiated, and the output voltage ramps
up between T 4 and T 5 .
COMP/EN
Soft-Start and Pre-Biased Outputs
The soft-start internally ramps the reference on the non-inverting
terminal of the error amp from 0V to 0.6V in a nominal 6.8ms.
The output voltage will follow the ramp from zero to its final value
in the same 6.8ms (the actual ramp seen on V OUT will be less
than the nominal time), due to some initialization timing
between T 3 and T 4 .
The ramp is created digitally, so there will be 64 small discrete
steps. There is no simple way to change this ramp rate externally.
After an initialization period (T 3 to T 4 ), the error amplifier (COMP/EN
pin) is enabled and begins to regulate the converter's output voltage
during soft-start. The oscillator's triangular waveform is compared to
the ramping error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitors. When the
internally generated soft-start voltage exceeds the reference voltage
(0.6V), the soft-start is complete and the output should be in
regulation at the expected voltage. This method provides a rapid and
ISET
VOUT
T T 0 0
T T 1 1
ISET
V OUT
controlled output voltage rise; there is no large inrush current
charging the output capacitors. The entire start-up sequence from
POR typically takes up to 17ms; up to 10.2ms for the delay and OCP
sample and 6.8ms for the soft-start ramp.
Figure 20 shows the normal curve for start-up; initialization
begins at T 0 , and the output ramps between T 1 and T 2 . If the
output is pre-biased to a voltage less than the expected value (as
shown Figure 21), neither internal MOSFET will turn on until the
soft-start ramp voltage exceeds the output; V OUT starts
seamlessly ramping from there.
FIGURE 18. I SET AND SOFT-START OPERATION
V OUT
START SWITCHING
T 2
T 2
T 3
T 4
T 5
COMP/EN
3.4ms
ISET
V OUT
3.4ms
T 0
T 1
FIGURE 20. NORMAL START-UP
FIGURE 19. I SET AND SOFT-START OPERATION
11
FN6999.3
July 26, 2012
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