参数资料
| 型号： | ISL8204MIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 14/21页 |
| 文件大小： | 0K |
| 描述： | IC BUCK SYNC ADJ 4A 15QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 500 |
| 类型： | 非隔离（POL） |
| 输出数： | 1 |
| 电压 - 输入（最小）： | 1V |
| 电压 - 输入（最大）： | 20V |
| Voltage - Output 1： | 0.6 ~ 6 V |
| 电流 - 输出（最大）： | 4A |
| 电源（瓦） - 制造商系列： | 24W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 15-BQFN |
| 尺寸/尺寸： | 0.59" L x 0.59" W x 0.14" H（15.0mm x 15.0mm x 3.5mm） |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 85°C |
| 效率： | 95% |
| 电源（瓦特）- 最大： | 24W |
ISL8204M, ISL8206M
Δ V
allowed for long-term reliability reasons, but transitions through
it to voltages above 6.5V are acceptable.
There is an internal 5V regulator for bias, which turns on between
5.5V and 6.5V. Some of the delay after POR is there to allow a
typical power supply to ramp-up past 6.5V before the soft-start
ramps begins. This prevents a disturbance on the output, due to
the internal regulator turning on or off. If the transition is slow (not
a step change), the disturbance should be minimal. Thus, while the
recommendation is to not have the output enabled during the
transition through this region, it may be acceptable. The user
should monitor the output for their application to see if there is any
problem. If P VCC powers up first and V IN is not present by the time
the initialization is done, then the soft-start will not be able to
ramp the output, and the output will later follow part of the V IN
ramp when it is applied. If this is not desired, then change the
sequencing of the supplies, or use the COMP/EN pin to disable
V OUT until both supplies are ready.
Figure 24 shows a simple sequencer for this situation. If P VCC
powers up first, Q 1 will be off, and R 3 pulling to P VCC will turn Q 2
on, keeping the ISL8204M, ISL8206M in shut-down. When V IN
turns on, the resistor divider R 1 and R 2 determine when Q 1 turns
on, which will turn off Q 2 and release the shut-down. If V IN powers
up first, Q 1 will be on, turning Q 2 off; so the ISL8204M,
ISL8206M will start-up as soon as P VCC comes up. The V ENDIS trip
point is 0.4V nominal, so a wide variety of N-MOSFET or NPN BJT
or even some logic IC's can be used as Q 1 or Q 2 . However, Q 2
must be low leakage when off (open-drain or open-collector) so
as not to interfere with the COMP output. Q 2 should also be
placed near the COMP/EN pin.
V IN PVCC
Switching Frequency
The switching frequency is a fixed 600kHz clock, which is
determined by the internal oscillator. However, all of the other
timing mentioned (POR delay, OCP sample, soft-start, etc.) is
independent of the clock frequency (unless otherwise noted).
Selection of the Input Capacitor
The input filter capacitor should be based on how much ripple
the supply can tolerate on the DC input line. The larger the
capacitor, the less ripple expected but consideration should be
taken for the higher surge current during power-up. The
ISL8204M, ISL8206M provides the soft-start function that
controls and limits the current surge. The value of the input
capacitor can be calculated by Equation 5:
I IN × Δ t
C IN = ------------------- (EQ. 5)
Where:
C IN is the input capacitance (μF)
I IN is the input current (A)
Δ t is the turn on time of the high-side switch (μs)
Δ V is the allowable peak-to-peak voltage (V)
In addition to the bulk capacitance, some low Equivalent Series
Inductance (ESL) ceramic capacitance is recommended to
decouple between the drain terminal of the high side MOSFET
and the source terminal of the low side MOSFET. This is used to
reduce the voltage ringing created by the switching current
across parasitic circuit elements.
R 1
R 3
TO COMP/EN
Output Capacitors
The ISL8204M, ISL8206M is designed for low output voltage
ripple. The output voltage ripple and transient requirements can
be met with bulk output capacitors (C OUT ) with low enough
Equivalent Series Resistance (ESR). C OUT can be a low ESR
tantalum capacitor, a low ESR polymer capacitor or a ceramic
R 2
Q 1
Q 2
capacitor. The typical capacitance is 330μF and decoupled
ceramic output capacitors are used. The internally optimized
loop compensation provides sufficient stability margins for all
ceramic capacitor applications with a recommended total value
FIGURE 24. SEQUENCE CIRCUIT
The V IN range can be as low as ~1V (for V OUT as low as the 0.6V
reference) and as high as 20V. There are some restrictions for
running high V IN voltage. The maximum PHASE voltage is 30V.
V IN + P VCC + any ringing or other transients on the PHASE pin
must be less than 30V. If V IN is 20V, it is recommended to limit
P VCC to 5V.
14
of 400μF. Additional output filtering may be needed if further
reduction of output ripple or dynamic transient spike is required.
FN6999.3
July 26, 2012
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| ISL8206M | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Complete High Efficiency DC/DC Power Module |
| ISL8206MEVAL1Z | 功能描述:电源管理IC开发工具 ISL8206 EVAL BRD 1 ROHS CMPL MOD RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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| ISL8206MIRZ-T | 功能描述:DC/DC转换器 ST& ALONE 6A DC/DC DWN PWR SUPPLY MOD RoHS:否 制造商:Murata 产品: 输出功率: 输入电压范围:3.6 V to 5.5 V 输入电压（标称）: 输出端数量:1 输出电压（通道 1）:3.3 V 输出电流（通道 1）:600 mA 输出电压（通道 2）: 输出电流（通道 2）: 安装风格:SMD/SMT 封装 / 箱体尺寸: |
| ISL8216MEVAL1Z | 功能描述:电源管理IC开发工具 ISL8216M EVALUATION BOARD 1 - 25 Ld HDA - RoHS COMPLIAN RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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