参数资料
型号: ISL8204MIRZ-T
厂商: Intersil
文件页数: 13/21页
文件大小: 0K
描述: IC BUCK SYNC ADJ 4A 15QFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 500
类型: 非隔离(POL)
输出数: 1
电压 - 输入(最小): 1V
电压 - 输入(最大): 20V
Voltage - Output 1: 0.6 ~ 6 V
电流 - 输出(最大): 4A
电源(瓦) - 制造商系列: 24W
安装类型: 表面贴装
封装/外壳: 15-BQFN
尺寸/尺寸: 0.59" L x 0.59" W x 0.14" H(15.0mm x 15.0mm x 3.5mm)
包装: 带卷 (TR)
工作温度: -40°C ~ 85°C
效率: 95%
电源(瓦特)- 最大: 24W
ISL8204M, ISL8206M
R SET-EX × R SET-IN
I PEAK > I OUT ( MAX ) + -------------
( Δ I L )
(EQ. 4)
r DS(ON) is typically 15m Ω @ (V PVCC = V GS = 10V, I DS = 15A) and
18m Ω @ (V PVCC = V GS = 4.5V, I DS = 15A).
Note: ISL8204M, ISL8206M has integrated 4.12k Ω/ 2.87k Ω
resistance (R SET-IN ). Therefore, the equivalent resistance of R SET
can be expressed in Equation 3:
R SET = ------------------------------------------------------- (EQ. 3)
R SET-EX + R SET-IN
The scale factor of 2 doubles the trip point of the MOSFET voltage
drop, compared to the setting on the R SET resistor. The OC trip
point varies in a system mainly due to the MOSFET r DS(ON)
variations (i.e. over process, current and temperature). To avoid
overcurrent tripping in the normal operating load range, find the
R SET resistor from Equation 3, and use the following values:
1. The maximum r DS(ON) at the highest junction temperature
2. The minimum I SET from the “Electrical Specifications” table
on page 3.
3. Determine I PEAK for:
2
where Δ I L is the output inductor ripple current. In a high input
voltage, high output voltage application, such as 20V input to 5V
output, the inductor ripple becomes excessive due to the fix
internal inductor value. In such applications, the output current will
be limited from the rating to approximately 70% of the module’s
rated current.
The relationships between the external R SET values and the
typical output current I OUT(MAX) OCP levels for ISL8206M are as
follows:
likely be different at a lower input voltage. Another factor is the
digital nature of the soft-start ramp. On each discrete voltage step,
there is in effect, a small load transient and a current spike to
charge the output capacitors. The height of the current spike is not
controlled, however, it is affected by the step size of the output and
the value of the output capacitors, as well as the internal error
amp compensation. Therefore, it is possible to trip the overcurrent
with inrush current, in addition to the normal load and ripple
considerations.
Figure 23 shows the output response during a retry of an output
shorted to PGND. At time T 0 , the output has been turned off due to
sensing an overcurrent condition. There are two internal soft-start
delay cycles (T 1 and T 2 ) to allow the MOSFETs to cool down in order
to keep the average power dissipation in retry at an acceptable
level. At time T 2 , the output starts a normal soft-start cycle, and
the output tries to ramp. If the short is still applied and the current
reaches the I SET trip point any time during the soft-start ramp
period, the output will shut off and return to time T 0 for another
delay cycle. The retry period is thus two dummy soft-start cycles
plus one variable (which depends on how long it takes to trip the
sensor each time). Figure 23 shows an example where the output
gets about half-way up before shutting down; therefore, the retry
(or hiccup) time will be around 17ms. The minimum should be
nominally 13.6ms and the maximum 20.4ms. If the short
condition is finally removed, the output should ramp up normally
on the next T 2 cycle.
R SET
( Ω )
TABLE 3.
OCP (A) @
V IN = 12V,
P VCC = 5V
OCP (A) @
V IN = 12V
P VCC = 12V
T 0
T 1
T 2
OPEN
50k Ω
20k Ω
10k Ω
5k Ω
8.1
7.5
6.6
5.5
4.4
8.8
8.1
7.4
6.4
5.0
~6.8ms
~6.8ms
V OUT
FIGURE 23. OVERCURRENT RETRY OPERATION
The range of allowable voltages detected (2 x I SET x R SET ) is 0mV to
475mV. If the voltage drop across R SET is set too low, the following
conditions may occur: (1) Continuous OCP tripping and retry and
(2) It may be overly sensitive to system noise and inrush current
spikes, so it should be avoided. The maximum usable setting is
around 0.2V across R SET (0.4V across the MOSFET); values above
this might disable the protection. Any voltage drop across R SET
that is greater than 0.3V (0.6V MOSFET trip point) will disable the
OCP. Note that conditions during power-up or during a retry may
look different than normal operation. During power-up in a 12V
system, the ISL8204M, ISL8206M starts operation just above 4V;
if the supply ramp is slow, the soft-start ramp might be over well
before 12V is reached. Therefore, with low side gate drive voltages,
the r DS(ON) of the MOSFET will be higher during power-up,
effectively lowering the OCP trip. In addition, the ripple current will
13
Starting up into a shorted load looks the same as a retry into that
same shorted load. In both cases, OCP is always enabled during
soft-start; once it trips, it will go into retry (hiccup) mode. The
retry cycle will always have two dummy time-outs, plus whatever
fraction of the real soft-start time passes before the detection
and shutoff. At that point, the logic immediately starts a new two
dummy cycle time-out.
Input Voltage Considerations
Figure 16 shows a standard configuration where P VCC is either 5V
(±10%) or 12V (±20%). In each case, the gate drivers use the
P VCC voltage for low side gate and high side gate driver. In
addition, P VCC is allowed to work anywhere from 6.5V up to the
14.4V maximum. The P VCC range between 5.5V and 6.5V is not
FN6999.3
July 26, 2012
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