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参数资料
| 型号： | ISL8502AEVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ISL8502 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 4.4V |
| 电流 - 输出： | 2A |
| 输入电压： | 5V，5.5 ~ 14 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 500kHz ~ 1.2MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板，文档 |
| 已用 IC / 零件： | ISL8502 |
ISL8502A
R T [ k Ω ] = ------------------------------
(EQ. 1)
Functional Pin Descriptions
PGOOD (Pin 1)
PGOOD is an open drain output that pulls to low if the output
goes out of regulation or a fault is detected. PGOOD is equipped
with a fixed delay upon output power-up. The PGOOD Rising
Delay specification is measured at 500 kHz from the point where
V OUT reaches regulation to the point where PGOOD rises. This
delay is reversely proportional to the switching frequency.
SGND (Pin 2)
The SGND terminal of the ISL8502A provides the return path for
the control and monitor portions of the IC.
EN (Pin 3)
The Enable pin is a bi-directional pin. If the voltage on this pin
exceeds the enable threshold voltage, the part is enabled. If a fault
is detected, the EN pin is pulled low via internal circuitry for a
duration of four soft-start periods. For automatic start-up, use 10k Ω
to 100k Ω pull-up resistor connecting to VCC.
SYNCH (Pin 4)
SYNCH is a bi-directional pin used to synchronize slave devices to
the master device. As a master device, this pin outputs the clock
signal to which the slave devices synchronize. As a slave device,
this pin is an input to receive the clock signal from the master
device.
If configured as a slave device, the ISL8502A is disabled if there
is no clock signal from the master device on the SYNCH pin.
Leave this pin unconnected if the IC is used in stand-alone
operation.
M/S (Pin 5)
As a slave device, tie a 5k Ω resistor between the M/S pin and
ground.
As a master or a stand-alone device, tie the M/S pin directly to
the VCC pin. Do not short the M/S pin to GND.
FS (Pin 6)
The FS pin provides oscillator switching frequency adjustment. By
placing a resistor (R T ) from the FS pin to GND, the switching
frequency can be programmed as desired between 500kHz and
1.2MHz as shown in Equation 1.
48000
f OSC [ kHz ]
Tying the FS pin to the VCC pin forces the switching frequency to
800kHz.
Using resistors with values below 40k Ω (1.2MHz) or with values
higher than 97k Ω (500kHz) may damage the ISL8502A.
COMP (Pin 7) and FB (Pin 8)
The switching regulator employs a single voltage control loop.
The FB pin is the negative input to the voltage loop error
amplifier. The output voltage is set by an external resistor divider
connected to FB. With a properly selected divider, the output
13
voltage can be set to any voltage between the power rail
(reduced by converter losses) and the 0.6V reference. Loop
compensation is achieved by connecting an AC network across
the COMP pin and the FB pin. The FB pin is also monitored for
undervoltage events.
SS (Pin 9)
Connect a capacitor from the SS pin to ground. This capacitor,
along with an internal 30μA current source, sets the soft-start
interval of the converter, t SS , as shown in Equation 2.
C SS [ μ F ] = 50 ? t SS [ S ] (EQ. 2)
PGND (Pins 10-13)
The PGND pins are used as the ground connection of the power
train.
PHASE (Pins 14-17)
The PHASE pins are the PHASE node connections to the inductor.
These pins are connected to the source of the control MOSFET
and the drain of the synchronous MOSFET.
VIN (Pins 18-21)
Connect the input rail to the VIN pins. These pins are the input to
the regulator as well as the source for the internal linear
regulator that supplies the bias for the IC.
It is recommended that the DC voltage applied to the VIN pins
does not exceed 14V. This recommendation allows for transient
spikes and voltage ringing to occur while not exceeding Absolute
Maximum Ratings.
BOOT (Pin 22)
The BOOT pin provides ground-referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive the internal N-channel MOSFET. The boot
diode is included within the ISL8502A.
PVCC (Pin 23)
The PVCC pin is the output of the internal linear regulator that
supplies the bias and gate voltage for the IC. A minimum 4.7μF
decoupling capacitor is recommended.
VCC (Pin 24)
The VCC pin supplies the bias voltage for the IC. This pin should
be tied to the PVCC pin through an RC low pass filter. A 10 Ω
resistor and 0.1μF capacitor are recommended.
Functional Description
Initialization
The ISL8502A automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continuously monitors
the voltage on the VCC pin. If the voltage on the EN pin exceeds
its rising threshold, then the POR function initiates soft-start
operation after the bias voltage has exceeded the POR threshold.
FN7940.0
October 21, 2011
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