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| 型号： | ISL8502AEVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ISL8502 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 4.4V |
| 电流 - 输出： | 2A |
| 输入电压： | 5V，5.5 ~ 14 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 500kHz ~ 1.2MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板，文档 |
| 已用 IC / 零件： | ISL8502 |
ISL8502A
(f 0dB ) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f 0dB and 180
degrees. Equation 12 relates the compensation network’s poles,
zeros, and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 and C 3 ) in
Figure 36. Use these guidelines for locating the poles and zeros
of the compensation network:
100
80
60
40
20LOG
f Z1 f Z2
f P1
f P2
OPEN LOOP
ERROR AMP GAIN
1. Pick Gain (R 2 /R 1 ) for desired converter bandwidth.
2. Place first zero below filter’s double pole (~75% F LC ).
3. Place second zero at filter’s double pole.
4. Place first pole at ESR Zero.
5. Place second pole at half the switching frequency.
20
0
-20
-40
-60
(R 2 /R 1 )
MODULATOR
GAIN
10 100
1k
f LC
10k
20LOG
(V IN / Δ V OSC )
f ESR
100k 1M
COMPENSATION
GAIN
CLOSED LOOP
GAIN
10M
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin; repeat if necessary.
Compensation Break Frequency Equations
FREQUENCY (Hz)
FIGURE 37. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Layout Considerations
f Z1 = ------------------------------------
f Z2 = -------------------------------------------------------
f P1 = ---------------------------------------------------------
2 π x R 2 x ? ?
? C 1 x C 2 ?
f P2 = ------------------------------------
1
2 π x R 2 x C 1
1
2 π x ( R 1 + R 3 ) x C 3
1
----------------------
? C 1 + C 2 ?
1
2 π x R 3 x C 3
(EQ. 12)
Layout is very important in high frequency switching converter
design. With power devices switching efficiently between 500kHz
and 1.2MHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage spikes
can degrade efficiency, radiate noise into the circuit, and lead to
device overvoltage stress. Careful component layout and printed
Figure 37 shows an asymptotic plot of the DC/DC converter gain
vs frequency. The actual modulator gain has a high gain peak
due to the high Q factor of the output filter and is not shown in
Figure 37. Using the guidelines provided should give a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F P2 with the capabilities of the error
amplifier. The closed loop gain is constructed on the graph of
Figure 37 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying the
modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks, Z FB
and Z IN , to provide a stable, high bandwidth (BW) overall loop. A
stable control loop has a gain crossing with -20dB/decade slope
and a phase margin greater than +45°. Include worst-case
component variations when determining phase margin. A more
detailed explanation of voltage mode control of a buck regulator
can be found in Tech Brief TB417 , entitled “Designing Stable
Compensation Networks for Single Phase Voltage Mode Buck
Regulators.”
17
circuit board design minimize these voltage spikes.
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET and
is picked up by the lower MOSFET. Any parasitic inductance in the
switched current path generates a large voltage spike during the
switching interval. Careful component selection, tight layout of
the critical components, and short, wide traces minimize the
magnitude of voltage spikes.
There are two sets of critical components in the ISL8502A
switching converter. The switching components are the most
critical because they switch large amounts of energy and
therefore tend to generate large amounts of noise. Next are the
small signal components, which connect to sensitive nodes or
supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 38
shows the connections of the critical components in the
converter. Note that capacitors C IN and C OUT could each
represent numerous physical capacitors. Dedicate one solid layer
(usually a middle layer of the PC board) for a ground plane, and
make all critical component ground connections with vias to this
layer. Dedicate another solid layer as a power plane, and break
this plane into smaller islands of common voltage levels. Keep
the metal runs from the PHASE terminals to the output inductor
short. The power plane should support the input power and
output power nodes. Use copper-filled polygons on the top and
bottom circuit layers for the phase nodes. Use the remaining
printed circuit layers for small signal wiring. The wiring traces
from the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
In order to dissipate heat generated by the internal V TT LDO, the
ground pad, pin 29, should be connected to the internal ground
plane through at least five vias. This allows heat to move away
FN7940.0
October 21, 2011
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