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参数资料
| 型号： | ISL8510IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 15/21页 |
| 文件大小： | 0K |
| 描述： | IC REG DL BUCK/LINEAR 24-QFN |
| 标准包装： | 6,000 |
| 拓扑： | 降压（降压）（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 500kHz |
| 电压/电流 - 输出 1： | 0.6 V ~ 20 V，1A |
| 电压/电流 - 输出 2： | 0.6 V ~ 4.2 V，500mA |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 5V，5.5 V ~ 25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 带卷 (TR) |
ISL8510
begins ramping linearly from ground until the voltage across
the soft-start capacitor reaches 3.0V. This linear ramp is
applied to the non-inverting input of the internal error
amplifier and overrides the nominal 0.6V reference. The
R1
V OUT
output voltage reaches its regulation value when the
soft-start capacitor voltage reaches 1.6V. Connect a
capacitor from SS pin to ground. This capacitor, along with
an internal 30μA current source sets the soft-start interval of
the converter, t SS .
EA
0.6V
REFERENCE
R2
C SS [ μ F ] = 50 ? t SS [ S ]
(EQ. 1)
FIGURE 29. EXTERNAL RESISTOR DIVIDER
Upon disabling, the SS pin voltage will discharge to zero
voltage.
Power-Good
PG_PWM is an open-drain output of a window comparator that
continuously monitors the buck regulator output voltage.
PG_PWM is actively held low when EN_PWM is low and
during the buck regulator soft-start period. After the soft-start
period terminates, PG_PWM becomes high impedance as long
as the output voltage is within ±10% of the nominal regulation
voltage set by FB_PWM. When V OUT drops 10% below or
rises 10% above the nominal regulation voltage, the ISL8510
pulls PG_PWM low. Any fault condition forces PG_PWM low
until the fault condition is cleared by attempts to soft-start. For
logic level output voltages, connect an external pull-up resistor
between PG_PWM and VCC. A 100k resistor works well in
most applications. Note that the PG_PWM window detector is
completely independent of the undervoltage protection fault
detectors and the state of LDO output.
PG_LDO is an open drain pull-down NMOS output that will
sink 1mA at 0.3V max. It goes to the active low state if the
LDO output is out of regulation by a value greater than 15%.
When the LDO is disabled, the output is active low.
Output Voltage Selection
All three regulator output voltages can be programmed using
external resistor dividers that scale the voltage feedback
relative to the internal reference voltage. The scaled voltage
is fed back to the inverting input of the error amplifier (refer
to Figure 29).
The output voltage programming resistor, R 2 , will depend on
the value chosen for the feedback resistor, R 1 , and the
desired output voltage, V OUT , of the regulator (see Equation 2).
The value for the feedback resistor is typically between 1k Ω
The buck output can be programmed as high as 20V. Proper
heatsinking must be provided to insure that the junction
temperature does not exceed +125°C.
When the output is set greater than 3.6V, it is recommended
to pre-load at least 1mA and make sure that the input rise
time is much faster than the V OUT1 rise time. This allows the
BOOT capacitor adequate time to charge for proper
operation.
Protection Features
The ISL8510 limits current in all on-chip power devices to
limit on-chip power dissipation. Overcurrent limits on all three
regulators protect internal power devices from excessive
thermal damage. Undervoltage protection circuitry on the
buck regulator provides a second layer of protection for the
internal power device under high current conditions.
Buck Regulator Overcurrent Protection
During the PWM on-time, the current through the internal
switching MOSFET is sampled and scaled through an
internal pilot device. The sampled current is compared to a
nominal 2A overcurrent limit. If the sampled current exceeds
the overcurrent limit reference level, an internal overcurrent
fault counter is set to 1 and an internal flag is set. The
internal power MOSFET is immediately turned off and will
not be turned on again until the next switching cycle.
The protection circuitry continues to monitor the current and
turns off the internal MOSFET as described. If the
overcurrent condition persists for four sequential clock
cycles, the overcurrent fault counter overflows indicating an
overcurrent fault condition exists. The regulator is shut down
and power-good goes low. If the overcurrent condition clears
prior to the counter reaching four consecutive cycles, the
internal flag and counter are reset.
R 2 = ----------------------------------
and 10k Ω .
R 1 ? 0.6V
V OUT – 0.6V
If the output voltage desired is 0.6V, then R 2 is left
unpopulated.
15
(EQ. 2)
The protection circuitry attempts to recover from the
overcurrent condition after waiting 4 soft-start cycles. The
internal overcurrent flag and counter are reset. A normal
soft-start cycle is attempted and normal operation continues
if the fault condition has cleared. If the overcurrent fault
counter overflows during soft-start, the converter shuts down
and this hiccup mode operation repeats.
FN6516.2
December 15, 2008
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