参数资料
型号: ISL8723EVAL1
厂商: Intersil
文件页数: 3/14页
文件大小: 0K
描述: EVAL BOARD 1 FOR ISL8723
产品培训模块: Solutions for Industrial Control Applications
标准包装: 1
系列: *
ISL8723, ISL8724
Pin Descriptions
(Continued)
PIN
PIN
#
NAME
FUNCTION
DESCRIPTION
18
DLY_OFF_A Gate Off Delay
Allows for programming the delay and sequence for V OUT turn-off through ENABLE/ENABLE via a
13
3
4
2
5
6
7
22
DLY_OFF_B
DLY_OFF_C
DLY_OFF_D
GATE_A
GATE_B
GATE_C
GATE_D
SYSRST
Timer Output
FET Gate Drive
Output
System Reset I/O
capacitor to ground. Each cap is charged with a 1μA internal current source to an internal reference
voltage causing the corresponding gate to be pulled down thus turning-off the FET.
Drives the external FETs with a 10μA current source to soft start ramp into the load. During sequence
off, 10μA is sunk from this pin to control the FET turn-off. During a turn-off due to a fault, the gate will
sink ~75mA to ensure a rapid turn-off.
As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low. This pin
can also be used to initiate the programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from
input signal on this pin being driven high to first GATE.
As an output when there is a UV condition this pin pulls low. If common to other SYSRST pins in a multiple
IC configuration it will cause immediate and unconditional latch-off of all other GATEs on all other ISL872x
sequencers.
This pin is released to go high once all UVLO and enable conditions are satisfied and is pulled low
concurrent with the last GATE being turned off after EN disabled.
9, 11
No Connect
No Connect
3
No Connect
FN6413.1
April 22, 2009
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