参数资料
型号: ISL89165FBECZ
厂商: Intersil
文件页数: 11/15页
文件大小: 0K
描述: MOSFET DRIVER 2CH 6A 8SOIC
标准包装: 980
配置: 低端
输入类型: 反相和非反相
延迟时间: 25ns
电流 - 峰: 6A
配置数: 2
输出数: 2
电源电压: 7.5 V ~ 16 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm Width)裸露焊盘
供应商设备封装: 8-SOIC-EP
包装: 管件
ISL89163, ISL89164, ISL89165
P D = 2 ? Q c ? freq ? V GS ? --------------------------------------------- + I DD ( freq ) ? V DD
DS ( ON )
R + r
Power Dissipation of the Driver
The power dissipation of the ISL89163, ISL89164, ISL89165 is
dominated by the losses associated with the gate charge of the
driven bridge FETs and the switching frequency. The internal bias
current also contributes to the total dissipation but is usually not
significant as compared to the gate charge losses.
12
Equation 2 shows calculating the power dissipation of the driver:
R gate
gate
(EQ. 2)
where:
freq = Switching frequency,
V GS = V DD bias of the ISL89163, ISL89164, ISL89165
10
8
6
4
2
V DS = 64V
V DS = 40V
Q c = Gate charge for V GS
I DD (freq) = Bias current at the switching frequency (see Figure 10)
r DS(ON) = ON-resistance of the driver
R gate = External gate resistance (if any).
Note that the gate power dissipation is proportionally shared with
the external gate resistor. Do not overlook the power dissipated
by the external gate resistor.
0
0 2 4 6 8 10 12 14 16 18 20 22
Q g, GATE CHARGE (nC)
FIGURE 19. MOSFET GATE CHARGE vs GATE VOLTAGE
24
Typical Application Circuits
This drive circuit provides primary to secondary line isolation. A
controller, on the primary side, is the source of the SR control
signals OUTLLN and OUTLRN signals. The secondary side signals,
Figure 19 illustrates how the gate charge varies with the gate
voltage in a typical power MOSFET. In this example, the total gate
charge for V gs = 10V is 21.5nC when V DS = 40V. This is the
charge that a driver must source to turn-on the MOSFET and
must sink to turn-off the MOSFET.
V1 and V2 are rectified by the dual diode, D9, to generate the
secondary side bias for U4. V1 and V3 are also inverted by Q100
and Q101 and the rising edges are delayed by R27/C10 and
R28/C9 respectively to generate the SR drive signals, LRN and
LLN. For more complete information on this SR drive circuit, and
other applications for the ISL89163, ISL89164, ISL89165, refer
to AN1603 “ISL6752/54EVAL1Z ZVS DC/DC Power Supply with
Synchronous Rectifiers User Guide”.
PWM
/OUTLLN
L
R
L
Primary to Secondary side self
biasing, Isolated SR drive
D9
R27
VBIAS
ENABLE
/OUTLRN
V2
V1
OUTLLN
V1
Q100
C123
R28
U4
LRN
R-SR
V2
LLN
EL7212
OUTLRN
Q101
V4
ISL89163
LSR
V3
T6
U4
V4
Red dashed lines point out the
turn-on delay of the SRs when
V3
C9
C10
LLN
LRN
11
PWM goes low
FN7707.3
March 7, 2012
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