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参数资料
| 型号： | ISL9443IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 15/23页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 32-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 电流模式 |
| 输出数： | 3 |
| 频率 - 最大： | 1.32MHz |
| 电源电压： | 4.5 V ~ 26 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | * |
| 包装： | * |
ISL9443
Functional Description
General Description
The ISL9443 integrates control circuits for three synchronous
buck converters. The three synchronous bucks operate
out-of-phase to substantially reduce the input ripple and thus
reduce the input filter requirements.
Each part has separate enable/disable control lines (EN/SS1,
EN23), which provide flexible power-up sequencing. The
soft-start time is programmable individually by adjusting the
soft-start capacitors connected from EN/SS1, TK/SS2 and
TK/SS3 respectively.
The valley current mode control scheme with input voltage
feed-forward ramp simplifies loop compensation and provides
excellent rejection to input voltage variation.
Input Voltage Range
The ISL9443 is designed to operate from input supplies
ranging from 4.5V to 28V.
The input voltage range can be effectively limited by the
available minimum PWM off time.
The internal LDO has an overcurrent limit of typically 150mA.
For better efficiency, connect VCC_5V to V IN for 5V ±10% input
applications.
Enable Signals and Soft-Start Operation
Typical applications for the ISL9443 use programmable
analog soft-start or the TK/SSx pins for tracking. The soft-start
time can be set by the value of the soft-start capacitors
connected from the EN/SS1 for PWM1 to ground and from
TK/SSx pins to ground for PWM2 and PWM3. Inrush current
during start-up can be alleviated by adjusting the soft-start
time.
After the VCC_5V pin reaches the UVLO threshold, the ISL9443
PWM1 soft-start circuitry becomes active. The internal 1.55μA
charge current begins charging up the soft-start capacitor
connected from the EN/SS1 pin to GND. The PWM1 output
remains inactive until voltage on the EN/SS1 pin reaches 1.3V.
As the voltage on the EN/SS1 pin rises from 1.3V to 2V, the
PWM1 reference voltage is clamped to the voltage on the
EN/SS1 pin minus 1.3V. PWM1 output voltage thus rises from
0V to regulation as EN/SS1 rises from 1.3V to 2V. Charging of
the soft-start capacitor continues until the voltage on the
EN/SS1 pin reaches 3.5V.
1 – t OFF ( min ) × Frequency ?
V IN ( min ) = ? ----------------------------------------------------------------------- ? + V d2 – V d1
?
? V OUT + V d1 ?
(EQ. 2)
Power sequencing can be achieved by using the EN23 and
TK/SSx pins. When the EN23 pin is pulled high, the internal
V IN ( max ) ≤ V OUT x ? ------------------------------------------------------------ ?
t ON ( min ) × Frequency ?
t SSx = 0.7V ? -------------------- ?
C SSx
? 1.55 μ A ?
Where,
Vd1 = sum of the parasitic voltage drops in the inductor
discharge path, including the lower FET, inductor and PC board.
Vd2 = sum of the voltage drops in the charging path, including
the upper FET, inductor and PC board resistances.
The maximum input voltage and minimum output voltage is
limited by the minimum on-time t ON(min) .
? V OUT ?
(EQ. 3)
?
Where t ON(min) = 100ns
Internal 5V Linear Regulator (VCC_5V)
All ISL9443 functions are internally powered from an on-chip,
low dropout 5V regulator. Bypass the linear regulator’s output
(VCC_5V) with a 4.7μF capacitor to the power ground. The
ISL9443 also employs an undervoltage lockout circuit that
disables all regulators when VCC_5V falls below 3.6V.
The internal LDO can source over 75mA to supply the IC, power
the low side gate drivers and charge the boot capacitors. When
driving large FETs at high switching frequency, little or no
regulator current may be available for external loads.
For example, a single large FET with 15nC total gate charge
requires 15nC x 300kHz = 4.5mA (15nC x 600kHz = 9mA).
Also, at higher input voltages with larger FETs, the power
dissipation across the internal 5V will increase. Excessive
dissipation across this regulator must be avoided to prevent
junction temperature rise. Thermal protection may be
triggered if die temperature increases above +150°C due to
excessive power dissipation.
shall be connected to the FBx pin. The output voltage value is
15
1.55μA charge current begins charging up the soft-start
capacitor connected from the TK/SSx pin to GND. The
respective reference voltage is clamped to the voltage on the
TK/SSx pin. Thus, PWM2 and PWM3 output voltages ramp
from 0V to regulation as voltage on TK/SS2 and TK/SS3 goes
up from 0V to 0.7V. Charging of the soft-start capacitors
continues until the voltage on the TK/SSx reaches 3.5V.
The typical soft-start time is set according to Equation 4:
(EQ. 4)
For PWM2 and PWM3, when the soft-start time set by external
C SS or tracking is less than 2ms, an internal soft-start circuit of
2ms takes over the soft-start. There is no internal soft-start for
PWM1.
PGOOD will toggle to high when all the outputs are up and in
regulation.
Pulling the EN23 low disables the PWM2 and PWM3 channels.
The TK/SSx pin will also be discharged to GND by internal
MOSFETs.
Output Voltage Programming
The ISL9443 provides a precision internal reference voltage to
set the output voltage. Based on this internal reference, the
output voltage can thus be set from 0.7V up to a level
determined by the input voltage, the maximum duty cycle, and
the conversion efficiency of the circuit.
A resistive divider from the output to ground sets the output
voltage of any PWM channel. The center point of the divider
FN7663.1
February 24, 2012
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