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| 型号： | ISL9443IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 16/23页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 32-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 电流模式 |
| 输出数： | 3 |
| 频率 - 最大： | 1.32MHz |
| 电源电压： | 4.5 V ~ 26 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | * |
| 包装： | * |
ISL9443
determined by Equation 5.
set by a resistor connected from the RT pin to GND according
V OUTx = 0.7V ? ---------------------- ?
? R2 ?
R1 + R2
(EQ. 5)
to Equation 1.
Frequency setting curve shown in Figure 20 assists in selecting
where R1 is the top resistor of the feedback divider network
and R2 is the bottom resistor connected from FBx to ground.
Tracking Operation
The PWM2 and PWM3 of the ISL9443 can be independently
set up to track the output of another PWM or an external
supply. In the following discussion, we refer to the voltage rail
to be tracked as the master rail while we refer to the voltage
rail that follows the master as the slave rail. To implement
tracking, an additional resistive divider is connected between
the master rail and ground. The center point of the divider shall
be connected to the TK/SSx pin of the slave PWM. The
resistive divider ratio sets the ramping ratio between the two
voltage rails. To implement coincident tracking, set the
the correct value for R T .
1250
1000
750
500
250
tracking resistive divider ratio exactly the same as the slave
rail output resistive divider given by Equation 5. Make sure that
the voltage at TK/SSx is greater than 0.7V when the master
rail reaches regulation.
0
0
20 40 60 80 100 120 140
R T (k ? )
FIGURE 20. R T vs SWITCHING FREQUENCY
160
180
To minimize the impact of the 1.55μA soft-start current on the
tracking function, it is recommended to use resistors of less
than 10k ? for the tracking resistive dividers.
When overcurrent-protection (OCP) is triggered for the slave
PWM channel, the internal minimum soft-start circuit
determines the OCP soft-start hiccup.
Light Load Efficiency Enhancement
When MODE/SYNC pin is tied to GND, the ISL9443 operates in
high efficiency diode emulation mode and pulse skipping
mode in light load condition. The inductor current is not
allowed to reverse (discontinuous operation). At very light
loads, the converter goes into diode emulation and triggers the
pulse skipping function. Here, the upper MOSFET remains off
until the output voltage drops to the point the error amplifier
output goes above the pulse skipping mode threshold.
The minimum t ON in the pulse skipping mode is 80ns, please
select the switching frequency so the PWM t ON is greater than
80ns at maximum VIN at no load.
Pre-biased Power-Up
The ISL9443 has the ability to soft-start with a pre-biased
output. The output voltage would not be yanked down during
pre-biased start-up. The PWM is not active until the soft-start
ramp reaches the output voltage times the resistive divider
ratio.
Overvoltage protection is alive during soft-starting.
Frequency Selection
Switching frequency selection is a trade-off between efficiency
and component size. Low switching frequency improves
efficiency by reducing MOSFET switching loss. To meet output
ripple and load transient requirements, operation at a low
switching frequency would require larger inductance and
output capacitance. The switching frequency of the ISL9443 is
16
Frequency Synchronization
The MODE/SYNC pin may be used to synchronize the ISL9443
with an external clock.
When the MODE/SYNC pin is connected to an external clock,
the ISL9443 will synchronize to this external clock at half of
the clock frequency. For proper operation, the frequency setting
resistor, R T , should be set according to Equation 1.
When frequency synchronization is in action, the controllers
will enter forced continuous current mode at light load.
Out-of-Phase Operation
To reduce input ripple current, the three PWM channels operate
180° out-of-phase. This reduces the input capacitor ripple current
requirements, reduces power supply-induced noise, and improves
EMI. This effectively helps to lower component cost, save board
space and reduce EMI.
Triple PWMs traditionally operate in-phase and turn on all three
upper FETs at the same time. The input capacitor must then
support the instantaneous current requirements of the three
switching regulators simultaneously, resulting in increased ripple
voltage and current. The higher RMS ripple current lowers the
efficiency due to the power loss associated with the ESR of the
input capacitor. This typically requires more low-ESR capacitors in
parallel to minimize the input voltage ripple and ESR-related
losses, or to meet the required ripple current specification.
With synchronized out-of-phase operation, the high-side MOSFETs
turn off 180° out-of-phase. The instantaneous input current
peaks of both regulators no longer overlap, resulting in reduced
RMS ripple current and input voltage ripple. This reduces the
required input capacitor ripple current rating, allowing fewer or
less expensive capacitors, and reducing the shielding
requirements for EMI. The typical operating curves show the
synchronized 180° out-of-phase operation.
FN7663.1
February 24, 2012
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