参数资料
型号: ISL9444IRZ
厂商: Intersil
文件页数: 4/24页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 40-QFN
标准包装: 60
PWM 型: 电流模式
输出数: 3
频率 - 最大: 1.32MHz
电源电压: 4.5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 管件
ISL9444
Pin Descriptions (Continued)
PIN
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
-
NAME
MODE/SYNC
ISEN3
PHASE3
BOOT3
UGATE3
LGATE3
PGND
CLKOUT
ISEN2
PHASE2
BOOT2
UGATE2
LGATE2
LGATE1
UGATE1
BOOT1
PHASE1
ISEN1
EPAD
FUNCTION
Dual function pin. Tie this pin to ground or VCC_5V for DEM or CCM operation mode selection. Connect this pin to ground
to select Diode Emulation Mode with pulse skipping at light load. While connected to VCC_5V, the controllers operate in
PWM Mode at light load.
Connect this pin to CLKOUT of another ISL9444 or an external clock for synchronization. The controller operates in PWM
at light load when synchronized with another ISL9444 or with an external clock.
Current signal input for PWM3. This pin is used to monitor the voltage drop across the lower MOSFET for current loop
feedback and overcurrent protection.
Phase node connection for PWM3. This pin is connected to the junction of the upper MOSFET’s source, output filter inductor,
and lower MOSFET’s drain. PHASE3 is the internal lower supply rail for the UGATE3.
Bootstrap pin to provide bias for PWM3 high-side driver. The positive terminal of the bootstrap capacitor connects to this
pin. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity.
High-side MOSFET gate driver output for PWM3.
Low-side MOSFET gate driver output for PWM3.
Power ground connection for all three PWM channels. This pin should be connected to the sources of the lower MOSFETs
and the (-) terminals of the external input capacitors
Clock signal output. The frequency of the clock signal is two times of the ISL9444 switching frequency set by the resistor
from RT to ground.
Current signal input for PWM2. This pin is used to monitor the voltage drop across the lower MOSFET for current loop
feedback and overcurrent protection.
Phase node connection for PWM2. This pin is connected to the junction of the upper MOSFET’s source, output filter inductor,
and lower MOSFET’s drain. PHASE2 is the internal lower supply rail for the UGATE2.
Bootstrap pin to provide bias for PWM2 high-side driver. The positive terminal of the bootstrap capacitor connects to this
pin. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity.
High-side MOSFET gate driver output for PWM2.
Low-side MOSFET gate driver output for PWM2.
Low-side MOSFET gate driver output for PWM1.
High-side MOSFET gate driver output for PWM1.
Bootstrap pin to provide bias for PWM1 high-side driver. The positive terminal of the bootstrap capacitor connects to this
pin. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity.
Phase node connection for PWM1. This pin is connected to the junction of the upper MOSFET’s source, output filter inductor,
and lower MOSFET’s drain. PHASE1 is the internal lower supply rail for the UGATE1.
Current signal input for PWM1. This pin is used to monitor the voltage drop across the lower MOSFET for current loop
feedback and overcurrent protection.
EPAD at ground potential. Solder it directly to GND plane for better thermal performance.
4
FN7665.3
May 29, 2012
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