参数资料
| 型号： | ISL97522IRZ-TK |
| 厂商： | Intersil |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | IC SUPPLY CTRL 4CH TFT-LCD 38QFN |
| 标准包装： | 1,000 |
| 应用： | LCD 电视机/监控器 |
| 电流 - 电源： | 3mA |
| 电源电压： | 4.5 V ~ 13.2 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-VFQFN 裸露焊盘 |
| 供应商设备封装： | 38-QFN（5x7） |
| 包装： | 带卷 (TR) |
ISL97522
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
PIN NAME
DRVN
DELB
FBW
VCC1
FBB
ISADJB
ILADJB
CINTB
DRVB
PGNDB
VHIB
NC
ISINB
VIN
EN
VHIL
LX
DRVL
PGNDP
FBL
ILADJL
CINTL
ISADJL
VDC
VDCP
NC
DRVP
NC
ACGND
VREF
FBP
CC2
CDLY
CTL
ENL
DRN
COM
SRC
PIN DESCRIPTION
Negative LDO base drive; open drain of an internal P-Channel MOSFET.
Active low control output for optional delay control for external A VDD P-Channel FET; when fault is detected, this pin
goes to high.
Negative LDO voltage feedback input pin; regulates to 0.2V nominal.
Supply input, connect to V IN .
A VDD regulator voltage feedback input pin; regulates to 1.2V nominal.
Current feedback adjust for A VDD .
With a resistor connected from this pin to GND sets the current limit of the external N-channel FET for A VDD.
A VDD integrator output, connect 2.2nF to analog GND.
Gate driver output for the external N-Channel switch.
Power GND for A VDD .
Internal Drive of Boost controller, Connect to VDCP.
Sense the drain voltage of the external N-channel FET and connected to the internal current limit comparator.
Main supply input.
Enable pin; high enable, low disabled.
V LOGIC boost strap mode.
V LOGIC switch connection.
Gate driver output for external N-channel switch.
Power GND.
V LOGIC regulator voltage feedback pin; regulates to 1.2V nominal.
With resistor connected from this pin to GND sets the current limit of the external N-channel FET.
V LOGIC integrator output, connect 2.2nF to analog GND.
Current feedback adjust for V LOGIC .
Positive supply for all internal analog circuits.
Positive supply for external N-Channel FET gate drives.
Positive LDO base drive; open drain of an internal N-Channel MOSFET.
Low noise signal ground.
Bandgap voltage bypass terminal; bypass with a 0.1μF to analog GND; can be used as charge pump reference.
Positive LDO voltage feedback input pin; regulates to 1.2V nominal.
Supply input, connect to V IN .
With a capacitor connect from this pin to GND, sets the delay time for start-up sequence and fault detection timeout.
Input control for switch output.
Enable pin for V LOGIC high enable; low disabled.
Lower reference voltage for switch output.
Switch output; when CTL = 1, COM is connected to SRC through a 15 Ω resistor, when CT: = 0, COM is connected
to DRN through a 30 Ω resistor.
Upper reference voltage for switch output.
8
FN7445.0
December 13, 2006
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