参数资料
| 型号： | ISL97649BIRZ |
| 厂商： | Intersil |
| 文件页数： | 14/20页 |
| 文件大小： | 0K |
| 描述： | IC POWER MANAGEMENT |
| 标准包装： | 75 |
| 系列： | * |
ISL97649B
I 2 C Serial Interface
The ISL97649B supports a bidirectional, bus-oriented protocol.
The protocol defines any device that sends data on to the bus as
a transmitter and the receiving device as the receiver. The device
controlling the transfer is a master, and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the DCP of the ISL97649B operates as a slave device
in all applications. The fall and rise times of the SDA and SCL
signals should be in the range listed in Table 5. Capacitive load
on I 2 C bus is also specified in Table 5.
All communication over the I 2 C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (Figure 17). On power-up
of the ISL97649B, the SDA pin is in input mode.
All I 2 C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
DCP continuously monitors the SDA and SCL lines for the START
condition and does not respond to any command until this
condition is met (Figure 17). A START condition is ignored during
the power-up sequence and during internal non-volatile write
cycles.
All I 2 C interface operations must be terminated by a STOP
TABLE 5. I 2 C INTERFACE SPECIFICATIONS
PARAMETER MIN TYP MAX
UNITS
condition, which is a LOW to HIGH transition of SDA while SCL is
high (Figure 17). A STOP condition at the end of a read operation,
or at the end of a write operation to volatile bytes only, places the
SDA and SCL Rise Time
SDA and SCL Fall Time
I 2 C Bus Capacitive Load
1000
300
400
ns
ns
pF
device in standby mode. A STOP condition during a write
operation to a non-volatile write byte initiates an internal
non-volatile write cycle. The device enters standby mode when
the internal non-volatile write cycle is completed.
Programming Supply Voltage
To program EEPROM bits, VGH must be higher than 12V when
AVDD is 8V. Outside these conditions, writing operations may not
be successful.
An Acknowledge (ACK) is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge receipt of the eight bits of data (Figure 18).
The ISL97649B DCP responds with an ACK after recognizing a
START condition followed by a valid identification byte (Byte 1). If
a master-receiver is involved in a transfer, it must signal the end
of data transmission to the slave-transmitter by not generating
an acknowledge on the last byte that was clocked out of the
slave. The ISL97649B releases the dataline to allow the master
to generate a STOP condition.
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 17. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
SDA OUTPUT FROM
1
8
9
HIGH IMPEDANCE
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
14
START
HIGH IMPEDANCE
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACK
FN7927.2
June 27, 2013
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