参数资料
| 型号： | ISL97649BIRZ |
| 厂商： | Intersil |
| 文件页数： | 6/20页 |
| 文件大小： | 0K |
| 描述： | IC POWER MANAGEMENT |
| 标准包装： | 75 |
| 系列： | * |
ISL97649B
Electrical Specifications VIN = ENABLE = 3.3V, AVDD = 8V, VON = 24V, VOFF = -6V. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 6)
(Note 7)
(Note 6)
UNITS
DIGITAL CONTROLLED POTENTIOMETER
SET VR
SET Voltage Resolution (Note 12)
8
Bits
SET DNL
SET ZSE
SET FSE
I RSET
AVDD to SET
SET Differential Nonlinearity
(Notes 8, 9, 14)
SET Zero-Scale Error (Note 10, 14)
SET Full-Scale Error (Note 11, 14)
RSET Current
AVDD to SET Voltage Attenuation
T A = +25°C
T A = +25°C
T A = +25°C
-
-
-
-
-
-
-
-
1:20
±1
±2
±8
100
-
LSB
LSB
LSB
μA
V/V
FAULT DETECTION THRESHOLD
V UVLO
OVP AVDD
T OFF
Undervoltage Lock-out Threshold
Boost Overvoltage Protection Off
Threshold to Shut Down IC (Note 13)
Thermal Shut-Down all channels
PV IN rising
PV IN falling
Temperature rising
2.25
2.125
15.0
2.33
2.20
15.5
153
2.41
2.27
16.0
V
V
V
°C
POWER SEQUENCE TIMING
I SS
Boost Soft-start Current
3
5.5
8
μA
Serial Interface Specifications
range, -40°C to +85°C.
For SCL and SDA, unless otherwise noted. Boldface limits apply over the operating temperature
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 14)
(Note 7)
(Note 14)
UNITS
f SCL
SCL Frequency (Note 6)
400
kHz
t iN
t AA
t BUF
t LOW
t HIGH
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
t HD:STO
C SCL
Pulse Width Suppression Time at SDA
and SCL Inputs (Note 6)
SCL Falling Edge to SDA Output Data
Valid
Time the Bus Must be Free Before the
Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Set-up Time
START Condition Hold Time
Input Data Set-up Time
Input Data Hold Time
STOP Condition Set-up Time
STOP Condition Hold Time for Read, or
Volatile Only Write
Capacitive on SCL
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V IN , until
SDA exits the 30% to 70% of V IN window.
SDA crossing 70% of V CC during a STOP
condition, to SDA crossing 70% of V IN during
the following START condition.
Measured at 30% of V IN crossing.
Measured at 70% of V IN crossing.
SCL rising edge to SDA falling edge, both
crossing 70% of V IN .
From SDA falling edge crossing 30% of V IN to
SCL falling edge crossing 70% of V IN .
From SDA exiting 30% to 70% of V IN window
to SCL rising edge crossing 30% of V IN .
From SCL rising edge crossing 70% of V IN to
SDA entering 30% to 70% of V IN window.
From SCL rising edge crossing 70% of V IN to
SDA rising edge crossing 30% of V IN .
From SDA rising edge to SCL falling edge,
both crossing 70% of V IN .
480
480
400
480
400
40
0
400
400
5
50
480
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
6
FN7927.2
June 27, 2013
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