参数资料
| 型号： | ISL97649BIRZ |
| 厂商： | Intersil |
| 文件页数： | 2/20页 |
| 文件大小： | 0K |
| 描述： | IC POWER MANAGEMENT |
| 标准包装： | 75 |
| 系列： | * |
ISL97649B
Application Diagram
VIN
C1,2
20μF
L1 10μH
LX
D1
SW
C4,5,6
30μF
AVDD
C7
0.1μF AVDD
VIN
R1
VIN
C32
0.1μF
EN
SS
AVDD BOOST
CONTROLLER
PGND
73.2k
FREQ SEQUENCER
FB
R2 8.06k
COMP
R12 5.5k C20 15nF
D4
Q1
VOFF
C11
0.1μF
C15
1μF
R6 1k
Z1
C16
1μF
AVDD
C8
47nF
SW
C10
47nF
VON
VFLK
D2
C9
1μF
D3
C12
1μF
VGH
VDPM
C17 1nF
C28
R9
10k
133k
R8
R7
83k
SCL
SDA
RSET
POS
DCP
GPM
CE
RE
VGHM
GPM_LO
C14 100pF
R5 100k
C18
0.47μF
0.1μF
VGH GPM
R22 22k
R26 100k
AVDD
VGH
AVDD
C19
0.47μF
V COM
AVDD
OUT
NEG
V COM OP
VOLTAGE
DETECTOR
VDIV
CD2
R14 85k
OPEN
R15 115k
Vin
THERMAL PAD
RESET
C26 1nF
R16
RESET
10k
VLOGIC
Pin Descriptions
PIN#
1
2
3
4
5
6
7
8
9
10
11
SYMBOL
FB
PGND
CE
RE
VGH
VGHM
VFLK
VDPM
GPM_LO
AVDD
SCL
DESCRIPTION
AVDD boost converter feedback. Connect to the center of a voltage divider between AVDD and GND to set the AVDD voltage.
Power ground
Gate Pulse Modulator delay control. Connect a capacitor between this pin and GND to set the delay time.
Gate Pulse Modulator slew control. Connect a resistor between this pin and GND to set the falling slew rate.
Gate Pulse Modulator high voltage input. Place a 0.1μF decoupling capacitor close to VGH pin.
Gate Pulse Modulator output for gate drive IC.
Gate Pulse Modulator control input from T CON .
Gate Pulse Modulator enable. Connect a capacitor from VDPM to GND to set the delay time before GPM is enabled. A current
source charges the capacitor on VDPM.
Gate Pulse Modulator low voltage input. Place a 0.47μF decoupling capacitor close to GPM_LO pin.
DCP and VCOM amplifier high voltage analog supply. Place a 0.47μF decoupling capacitor close to AVDD pin.
I 2 C compatible clock input
2
FN7927.2
June 27, 2013
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