参数资料
| 型号： | ISLA224S25IR1Z |
| 厂商： | Intersil |
| 文件页数： | 10/38页 |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 标准包装： | 1 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页
ISLA224S
18
FN7911.2
April 25, 2013
Analog Input
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit ADC. The ideal
full-scale input voltage is 2.0V, centered at the VCM voltage as
shown in Figure 42.
Best performance is obtained when the analog inputs are driven
differentially. The common-mode output voltage, VCM, should be
used to properly bias the inputs as shown in Figures 43 through
45. An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate frequency
(IF) inputs. Two different transformer input schemes are shown in
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the ISLA224S is 600
Ω.
The SHA design uses a switched capacitor input stage (see
Figure 58), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes a
disturbance at the input, which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 2:1 or 1:1
transformer and low shunt resistance are recommended for
optimal performance.
A differential amplifier, as shown in the simplified block diagram
in Figure 45, can be used in applications that require
DC-coupling. In this configuration, the amplifier will typically
dominate the achievable SNR and distortion performance.
Intersil’s new ISL552xx differential amplifier family can also be
used in certain AC applications with minimal performance
degradation. Contact the factory for more information.
When an over range occurs, the data sample output bits are held
at full scale (all 0’s or all 1’s), thus allowing the detection of this
condition in the receiver device.
Clock Input
The clock input circuit is a differential pair (see Figure 59). Driving
these inputs with a high level (up to 1.8VP-P on each input) sine or
square wave will provide the lowest jitter performance. A
transformer with 4:1 impedance ratio will provide increased drive
levels. The clock input is functional with AC-coupled LVDS, LVPECL,
and CML drive levels. To maintain the lowest possible aperture
jitter, it is recommended to have high slew rate at the zero crossing
of the differential clock input signal.
The recommended drive circuit is shown in Figure 46. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 through a Thevenin equivalent of 10kΩ to facilitate AC
coupling.
A selectable 2x or 4x frequency divider is provided in series with the
clock input. The divider can be used in the 2x mode with a sample
clock equal to twice the desired sample rate or in 4x mode with a
sample clock equal to four times the desired sample rate. Use of the
2x or 4x frequency divider enables the use of the Phase Slip feature,
which enables the system to be able to select the phase of the
divide by 2 or divide by 4 that causes the ADC to sample the
analog input.
FIGURE 42. ANALOG INPUT RANGE
1.0
1.8
0.6
0.2
1.4
VINP
VINN
VCM
1.0V
FIGURE 43. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
ADT1-1WT
0.1F
ADC
VCM
ADT1-1WT
1000pF
FIGURE 44. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
ADC
VCM
1000pF
TX-2-5-1
ADTL1-12
FIGURE 45. DIFFERENTIAL AMPLIFIER INPUT
ADC
FIGURE 46. RECOMMENDED CLOCK DRIVE
TC4-19G2+
1000pF
CLKP
CLKN
0.01F
200
1000pF
相关PDF资料 |
PDF描述 |
|---|---|
| KAD2708C-27Q68 | IC ADC 8BIT 275MSPS PAR 68-QFN |
| KAD2708L-27Q68 | IC ADC 8BIT 275MSPS PAR 68-QFN |
| KAD2710C-27Q68 | IC ADC 10BIT 275MSPS PAR 68-QFN |
| KAD2710L-21Q68 | IC ADC 10BIT 210MSPS SGL 68-QFN |
| KAD5510P-25Q48 | IC ADC 10BIT CMOS 250MSPS 48QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISLA224S25IR48EV1Z | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual 12-Bit, 250/200/125 MSPS JESD204B High Speed Serial Output ADC |
| ISLEM-BDGSTKEV1Z | 制造商:Intersil Corporation 功能描述:DAQ ON A STICK, E-MICRO STRAIN GAUGE, EVAL BOARD 1, ROHS COM - Bulk 制造商:Intersil Corporation 功能描述:EVAL BOARD FOR STRAIN GAUGE |
| ISLI2C-KIT | 制造商:Intersil Corporation 功能描述:ISLI2C - USB INTERFACE - Bulk |
| ISLN312AD3ST | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| ISLT1102 | 制造商:ISOCOM 制造商全称:ISOCOM 功能描述:ISLT1102 ( Long Creepage ) |
发布紧急采购，3分钟左右您将得到回复。