参数资料
| 型号： | ISLA224S25IR1Z |
| 厂商： | Intersil |
| 文件页数： | 11/38页 |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 标准包装： | 1 |
| 系列： | * |
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ISLA224S
19
FN7911.2
April 25, 2013
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 25. A delay-locked loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 52μs to regain lock at 250MSPS. The lock time is
inversely proportional to the sample rate.
The DLL has two ranges of operation, slow and fast. The slow
range can be used for ADC core sample rates between 40MSPS
and 100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate. The lane data
rate is related to the ADC core sample rate by a relationship that
is defined by the JESD204 transmitter configuration, and has
additional frequency constraints; see“JESD204 Transmitter” on
page 20 for additional details.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
illustrated in Figure 47.
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise as well. Internal aperture jitter is the uncertainty in
the sampling instant. The internal aperture jitter combines with
the input clock jitter in a root-sum-square fashion, since they are
not statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise sources,
then determines the achievable SNR.
Voltage Reference
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full-scale range of each ADC is proportional to
the reference voltage. The nominal value of the voltage reference
is 1.25V.
Digital Outputs
The digital outputs are in CML format, and feature analog and
digital characteristics compliant with the JESD204 standard
requirements.
Power Dissipation
The power dissipated by the device is dependent on the ADC
sample rate and the number of active lanes in the link. There is a
fixed bias current drawn from the analog supply for the ADC,
along with a fixed bias current drawn from the digital supply for
each active lane. The remaining power dissipation is linearly
related to the sample rate.
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the ADC is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation significantly while taking a very short time to return to
functionality. Sleep mode reduces power consumption drastically
while taking longer to return to functionality.
In Nap mode the JESD204 lanes will continue to produce valid
encoded data, allowing the link to remain active and thus return to
a functional state quickly. The data transmitted over the lanes in
nap mode is the last valid ADC sample, repeated until leaving nap
mode. The 8b/10b encoder’s running disparity will prevent the
potentially long time repetition of this last valid sample from
creating DC bias on the lane. In sleep mode the JESD204 lanes will
be deactivated to conserve power. Thus, sometime after wake up
code group alignment will be required to reestablish the link.
The input clock should remain running and at a fixed frequency
during Nap or Sleep, and CSB should be high. The JESD204 link
will only remain established during nap mode if the input clock
continues to remain stable during the nap period.
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2. Please note
that power on calibration occurs at power up time regardless of
the state of the NAPSLP pin; immediately following this power on
calibration routine the device will enter nap or sleep state if the
NAPSLP pin voltage dictates it is to do so.
The power-down mode can also be controlled through the SPI port,
which overrides the NAPSLP pin setting. However, if the ADC is
powered-on with the NAPSLP pin in either Nap or Sleep modes, the
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
SNR
20 log
10
1
2
πf
IN tJ
--------------------
=
(EQ. 1)
FIGURE 47. SNR vs CLOCK JITTER
tj = 100ps
tj = 10ps
tj = 1ps
tj = 0.1ps
10 BITS
12 BITS
14 BITS
50
55
60
65
70
75
80
85
90
95
100
1M
10M
100M
1G
SNR
(dB)
INPUT FREQUENCY (Hz)
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Nap
AVDD
Sleep
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