参数资料
| 型号： | ISLA224S25IR1Z |
| 厂商： | Intersil |
| 文件页数： | 18/38页 |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 标准包装： | 1 |
| 系列： | * |
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ISLA224S
25
FN7911.2
April 25, 2013
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The SPI
bus consists of chip select (CSB), serial clock (SCLK) serial data
output (SDO), and serial data input/output (SDIO). The maximum
SCLK rate is equal to the ADC sample rate (fSAMPLE) divided by 7
for write operations and fSAMPLE divided by 16 for reads. There is
no minimum SCLK rate.
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the serial data
input/output (SDIO) pin in three-wire mode. The state of the SDIO
pin is set automatically in the communication protocol
(described in the following). A dedicated serial data output pin
(SDO) can be activated by setting 0x00[7] high to allow operation
in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the ADC functioning as a slave. Multiple slave
devices can interface to a single master in three-wire mode only,
since the SDO output of an unaddressed device is asserted in
four wire mode.
The chip-select bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
devices are selected for reading at the same time, the results will
be indeterminate.
FIGURE 55. SPI READ
( 3
WIRE MODE )
(4
WIRE MODE)
W1
W0
A12
A9
A2
A1
D7
D6
D3
D2
D1
D7
D3
D2
D1
D0
A0
WRITING A READ COMMAND
READING DATA
D0
tH
tDVR
SPI READ
tHI
tCLK
tLO
tDHW
tDSW
tS
CSB
SCLK
SDIO
SDO
A11
A10
R/W
FIGURE 56. 2-BYTE TRANSFER
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
CSB STALLING
FIGURE 57. N-BYTE TRANSFER
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
LAST LEGAL
CSB STALLING
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相关代理商/技术参数 |
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