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| 型号： | ISPPAC-POWR604-01TN44E |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 5/30页 |
| 文件大小： | 0K |
| 描述： | IC ISP POWER MGR ANLG/LOG 44TQFP |
| 标准包装： | 160 |
| 系列： | ispPAC® |
| 应用： | 电源监控器，序列发生器 |
| 输入电压： | 0 V ~ 6 V |
| 电源电压： | 2.25 V ~ 5.5 V |
| 电流 - 电源： | 10mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LQFP |
| 供应商设备封装： | 44-TQFP（10x10） |
| 包装： | 托盘 |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页
Lattice Semiconductor
Pin Descriptions (Continued)
ispPAC-POWR604 Data Sheet
Number
42
43
44
Name
NC
NC
NC
—
—
—
Pin Type
—
—
—
Voltage Range
No Connect
No Connect
No Connect
Description
1. IN1...IN4 are digital inputs to the PLD. The thresholds for these pins are referenced by the voltage on VDDINP.
2. The open-drain outputs can be powered independently of VDD and pulled up as high as +6.0V (referenced to ground). Exception, CLK pin
26 can only be pulled as high as VDD.
3. VDDINP can be chosen independent of V DD. It applies only to the four logic inputs IN1-IN4.
4. The six VMON inputs can be biased independently of VDD. The six VMON inputs can be as high as 7.0V Max (referenced to ground).
5. CLK is the PLD clock output in master mode. It is re-routed as an input in slave mode. The clock mode is set in software during design time.
In output mode it is an open-drain type pin and requires an external pull-up resistor (pullup voltage must be ≤ V DD ). Multiple ispPAC-
POWR604 devices can be tied together with one acting as the master, the master can use the internal clock and the slave can be clocked
by the master. The slave needs to be set up using the clock as an input.
6. RESET is an active low INPUT pin, external pull-up resistor required. When driven low it resets all internal PLD ?ip-?ops to zero, and may
turn “ON” or “OFF” the output pins, depending on the polarity con?guration of the outputs in the PLD. If a reset function is needed for the
other devices on the board, the PLD inputs and outputs can be used to generate these signals. The RESET connected to the POR pin can
be used if multiple ispPAC-POWR604 devices are cascaded together in expansion mode or if a manual reset button is needed to reset the
PLD logic to the i nitial state. While using the ispPAC-POWR604 in hot-swap applications it is recommended that either the RESET pin be
connected to the POR pin, or connect a capacitor to ground (such that the time constant is 10 ms with the pull-up resistor) from the RESET
pin.
7. The CREF pin requires a 0.1μF capacitor to ground, near the device pin. This reference is used internally by the device. No additional
external circuitry should be connected to this pin.
8. The four digital outputs (pins 12-15) are named OUT5-OUT8 to match ispPAC-POWR1208 pin names and to allow easy design migration.
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses above those listed values may cause permanent
damage to the device. Functional operation of the device at these or any other conditions above those indicated in
the operating sections of this speci?cation is not implied.
Symbol
VDD
Parameter
Core supply voltage at pin
Conditions
—
Min.
-0.5
Max.
6.0
Units
V
VDD INP
V IN 2
VMON
V TRI
T S
T A
T SOL
1
Digital input supply voltage for IN1-IN4
Input voltage applied, digital inputs
Input voltage applied, V MON voltage monitor inputs
Tristated or open drain output, external voltage applied
(CLK pin 26 pull-up ≤ VDD).
Storage temperature
Ambient temperature with power applied
Maximum soldering temperature (10 sec. at 1/16 in.)
—
—
—
—
—
—
—
-0.5
-0.5
-0.5
-0.5
-65
-55
—
6.0
6.0
7.0
6.0
150
125
260
V
V
V
V
°C
°C
°C
1. V DDINP is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1μF capacitor to ground and supply the V DDINP pin with appropriate
supply voltage for the given input logic range.
2. Digital inputs are tolerant up to 5.5V, independent of the V DDINP voltage.
2-4
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISPPAC-POWR604-01TN44I | 功能描述:监控电路 PROGRAMMABLE PWR SUPPLY CONTR RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| ISPPAC-POWR60401TNE | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Sequencing Controller and Monitor |
| ISPPAC-POWR60401TNI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Sequencing Controller and Monitor |
| ispPAC-POWR605-01SN24I | 功能描述:监控电路 PROCESSORPM 6-SUPPLY SUPERVISOR RESET GEN RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| ispPAC-POWR607-01N32I | 功能描述:监控电路 Prec. Prog. Pwr Sppl y Seq. Mon. I RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
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