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| 型号： | ISPPAC-POWR6AT6-01S32I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 17/35页 |
| 文件大小： | 0K |
| 描述： | IC PWR MANAGER ISP GP 32-QFNS |
| 产品培训模块： | Power and Board Management Solutions |
| 标准包装： | 490 |
| 系列： | ispPAC® |
| 应用： | 电源控制器/监控器 |
| 输入电压： | -0.3 V ~ 5.9 V |
| 电源电压： | 2.8 V ~ 3.96 V |
| 电流 - 电源： | 10mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFNS（5x5） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
trim will begin and CLTLOCK/SMBA will only reassert when the trim process is complete. Contents of the I 2 C
cltlock_status register (0x00), however are not fully reset to initial conditions until the CLTLOCK/SMBA pin achieves
a reasserted state.
CAUTION: Issuing a RESET command through I 2 C or JTAG during the ispPAC-POWR6AT6 device operation,
results in the device aborting all operations and returning to the power-on reset state except for the one condition
mentioned above.
I 2 C/SMBUS Interface
I 2 C and SMBus are low-speed serial interface protocols designed to enable communications among a number of
devices on a circuit board. The ispPAC-POWR6AT6 supports a 7-bit addressing of the I 2 C communications proto-
col, as well as SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many types
of modern power management systems. Figure 3-12 shows a typical I 2 C con?guration, in which one or more isp-
PAC-POWR6AT6s are slaved to a supervisory microcontroller. SDA is used to carry data signals, while SCL pro-
vides a synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I 2 C address of
the POWR6AT6 is fully programmable through the JTAG port.
Figure 3-12. ispPAC-POWR6AT6 in I 2 C/SMBUS System
V+
SDA/SMDAT (DATA)
SCL/SMCLK (CLOCK)
SMBALERT
To Other
I 2 C
Devices
SDA
SCL
INTERRUPT
SDA
SCL
OUT5/
SMBA
SDA
SCL
OUT5/
SMBA
MICROPROCESSOR
(I 2 C MASTER)
ispPAC-POWR6AT6
(I 2 C SLAVE)
ispPAC-POWR6AT6
(I 2 C SLAVE)
In both the I 2 C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This mas-
ter device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices.
The ispPAC-POWR6AT6 is con?gured as a slave device, and cannot independently coordinate data transfers.
Each slave device on a given I 2 C bus is assigned a unique address. The ispPAC-POWR6AT6 implements the 7-bit
addressing portion of the standard. Any 7-bit address can be assigned to the ispPAC-POWR6AT6 device by pro-
gramming through JTAG. When selecting a device address, one should note that several addresses are reserved
by the I 2 C and/or SMBus standards, and should not be assigned to ispPAC-POWR6AT6 devices to assure bus
compatibility. Table 3-3 lists these reserved addresses.
3-17
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