参数资料
型号: ISPPAC-POWR6AT6-01S32I
厂商: Lattice Semiconductor Corporation
文件页数: 30/35页
文件大小: 0K
描述: IC PWR MANAGER ISP GP 32-QFNS
产品培训模块: Power and Board Management Solutions
标准包装: 490
系列: ispPAC®
应用: 电源控制器/监控器
输入电压: -0.3 V ~ 5.9 V
电源电压: 2.8 V ~ 3.96 V
电流 - 电源: 10mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFNS(5x5)
包装: 托盘
Lattice Semiconductor
Figure 3-27. ispPAC-POWR6AT6 ID Code
MSB
ispPAC-POWR6AT6 Data Sheet
LSB
XXXX / 0000 0001 1000 0000 / 0000 0100 001 / 1
Part Number
(16 bits)
0180h = ispPAC-POWR6AT6
JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
Version
(4 bits)
E 2 Configured
(11 bits)
Constant 1
(1 bit)
per 1149.1-1990
ispPAC-POWR6AT6 Speci?c Instructions
There are 15 unique instructions speci?ed by Lattice for the ispPAC-POWR6AT6. These instructions are primarily
used to interface to the various user registers and the E 2 CMOS non-volatile memory. Additional instructions are
used to control or monitor other features of the device. A brief description of each unique instruction is provided in
detail below, and the bit codes are found in Table 3-7.
BULK_ERASE - This instruction will bulk erase the ispPAC-POWR6AT6. The action occurs at the second rising
edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode
(PROGRAM_ENABLE instruction).
PROGRAM_SECURITY - This instruction is used to program the electronic security fuse (ESF) bit. Programming
the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE
instruction).
DISCHARGE - This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispPAC-POWR6AT6 for a read cycle.
PROGRAM_ENABLE - This instruction enables the programming mode of the ispPAC-POWR6AT6.
IDCODE - This instruction connects the output of the Identi?cation Code Data Shift (IDCODE) Register to TDO
(Figure 3-28), to support reading out the identi?cation code.
Figure 3-28. IDCODE Register
TDO
Bit
31
Bit
30
Bit
29
Bit
28
Bit
27
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
UES_READ - This instruction both reads the E 2 CMOS bits in the UES register and places the UES register
between the TDI and TDO pins (as shown in Figure 3-29), to support programming or reading of the user electronic
signature bits.
Figure 3-29. UES Register
TDO
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
UES_PROG - This instruction will program the content of the UES Register into the UES E 2 CMOS memory. The
device must already be in programming mode (PROGRAM_ ENABLE instruction).
PROGRAM_DISABLE - This instruction disables the programming mode of the ispPAC-POWR6A6. The Test-
Logic-Reset JTAG state can also be used to cancel the programming mode of the ispPAC-POWR6A6.
3-30
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