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| 型号： | ISPPAC-POWR6AT6-01S32I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 21/35页 |
| 文件大小： | 0K |
| 描述： | IC PWR MANAGER ISP GP 32-QFNS |
| 产品培训模块： | Power and Board Management Solutions |
| 标准包装： | 490 |
| 系列： | ispPAC® |
| 应用： | 电源控制器/监控器 |
| 输入电压： | -0.3 V ~ 5.9 V |
| 电源电压： | 2.8 V ~ 3.96 V |
| 电流 - 电源： | 10mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFNS（5x5） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
Writing a value to the ADC_MUX register to set the input attenuator and selector will automatically initiate a conver-
sion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.0) will be reset to 0. When the conver-
sion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by
performing two I 2 C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recom-
mended that the I 2 C master load a second conversion command only after the completion of the current conversion
command (Waiting for the DONE bit to be set to 1). An alternative would be to wait for a minimum speci?ed time
(see Tconvert value in the speci?cations) and disregard checking the DONE bit.
Note that if the I 2 C clock rate falls below 50kHz (see F I2C note in speci?cations), the only way to insure a valid ADC
conversion is to wait the minimum speci?ed time (Tconvert), as the operation of the DONE bit at clock rates lower
than that cannot be guaranteed. In other words, if the I 2 C clock rate is less than 50kHz, the DONE bit may or may
not assert even when a valid conversion result is available. Erroneous ADC readout results are also possible when-
ever the I 2 C clock is less than 50kHz and a second ADC convert is commanded before a full T CONVERT time period
has elapsed. Under these conditions, it is still possible to obtain valid results for the second conversion by reading
out the ADC low and high byte results twice in succession (read ADC_VALUE_LOW, read ADC_VALUE_HIGH,
then repeating the low and high byte reads). Only the second ADC readout value is reliably valid, however.
To insure every ADC conversion result is valid, preferred operation is to clock I 2 C at more than 50kHz and verify
DONE bit status or wait for the full T CONVERT time period between subsequent ADC convert commands. If an I 2 C
request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second
request is complete.
The UES word may also be read through the I 2 C interface, with the register mapping shown in Figure 3-17.
Figure 3-17. I 2 C Register Mapping for UES Bits
0x04 - UES_BYTE0 (Read Only)
UES7
b7
UES6
b6
UES5
b5
UES4
b4
UES3
b3
UES2
b2
UES1
b1
UES0
b0
0x05 - UES_BYTE1 (Read Only)
UES15
b7
UES14
b6
UES13
b5
UES12
b4
UES11
b3
UES10
b2
UES9
b1
UES8
b0
0x06 - UES_BYTE2 (Read Only)
UES23
b7
UES22
b6
UES21
b5
UES20
b4
UES19
b3
UES18
b2
UES17
b1
UES16
b0
0x07 - UES_BYTE3 (Read Only)
UES31
b7
UES30
b6
UES29
b5
UES28
b4
UES27
b3
UES26
b2
UES25
b1
UES24
b0
The I 2 C interface also provides the ability to initiate reset operations. The ispPAC-POWR6AT6 may be reset by issu-
ing a write of any value to the I 2 C RESET register (Figure 3-18). Refer to the RESET Command via JTAG or I 2 C
section of this data sheet for further information.
3-21
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