参数资料
| 型号： | IXDS502D1B |
| 厂商： | IXYS |
| 文件页数： | 4/11页 |
| 文件大小： | 0K |
| 描述： | IC GATE LS DRVR SGL 2A 6-DFN |
| 标准包装： | 121 |
| 类型： | 低端 |
| 输入类型： | 非反相 |
| 输出数： | 1 |
| 导通状态电阻： | 4 欧姆 |
| 电流 - 输出 / 通道： | 500mA |
| 电流 - 峰值输出： | 2A |
| 电源电压： | 4.5 V ~ 25 V |
| 工作温度： | -55°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-VFDFN |
| 供应商设备封装： | 6-DFN |
| 包装： | 盒 |
IXDR502 / IXDS502
Electrical Characteristics @ temperatures over -55 o C to 125 o C (3)
Unless otherwise noted, 4.5V ≤ V CC ≤ 22V , Tj < 150 o C
All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions .
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V IH
V IL
High input voltage
Low input voltage
4.5V ≤ V CC ≤ 15V
4.5V ≤ V CC ≤ 15V
3.5
0.8
V
V
V IN
Input voltage range
-5
V CC + 0.3
V
I IN
Input current
0V ≤ V IN ≤ V CC
-20
20
μ A
V OH
V OL
High output voltage
Low output voltage
V CC - 0.05
0.05
V
V
R OH
Output resistance
V CC = 15V
6
?
@ Output high
R OL
Output resistance
V CC = 15V
4
?
@ Output Low
I DC
Continuous output
0.3
A
current
t R
t F
t ONDLY
Rise time
Fall time
On-time propagation
C L =1000pF Vcc=15V
C L =1000pF Vcc=15V
C L =1000pF Vcc=15V
14
12
40
ns
ns
ns
delay
t OFFDLY
Off-time propagation
C L =1000pF Vcc=15V
35
ns
delay
V CC
I CC
Power supply voltage
Power supply current
V IN = 3.5V
V IN = 0V
V IN = + V CC , (4.5V ≤ V CC ≤ 18V)
4.5
15
1
0
22
3
10
10
V
mA
μ A
μ A
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
to highlight any specific performance limits within which the device is guaranteed to function.
* The following notes are meant to define the conditions for the θ J-A , θ J-C and θ J-S values:
1) The θ J-A (typ) is defined as junction to ambient. The θ J-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated
by the resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with
vertical boards and the values would be lower with forced convection. For the 6-Lead DFN package, the θ J-A value supposes the DFN
package is soldered on a PCB. The θ J-A (typ) is 200 ° C/W with no special provisions on the PCB, but because the center pad
provides a low thermal resistance to the die, it is easy to reduce the θ J-A by adding connected copper pads or traces on the PCB.
These can reduce the θ J-A (typ) to 125 ° C/W easily, and potentially even lower. The θ J-A for DFN on PCB without heatsink or thermal
management will vary significantly with size, construction, layout, materials, etc. This typical range tells the user what they are likely
to get if no thermal management is done.
2) θ J-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θ J-C values are generally
not published for the PDIP and SOIC packages. The θ J-C for the DFN packages are important to show the low thermal resistance from
junction to the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The θ J-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a
heatsink. The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily
available IMS in the U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was
assumed. The result was given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential
low thermal resistance for the DFN package.
Copyright ? 2007 IXYS CORPORATION All rights reserved
4
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