参数资料
型号: K4S281632D-TP7C
元件分类: DRAM
英文描述: 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封装: 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
文件页数: 3/9页
文件大小: 80K
代理商: K4S281632D-TP7C
CMOS SDRAM
K4S281632D
Rev. 0.1 Sept. 2001
The K4S281632D is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNG
′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock.
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2M x 16Bit x 4 Banks Synchronous DRAM
Bank Select
Data Input Register
2M x 16
S
e
n
s
e
A
M
P
O
u
tp
u
t
B
u
ffe
r
I/O
C
o
n
tr
o
l
Column Decoder
Latency & Burst Length
Programming Register
A
d
re
s
R
e
g
is
te
r
R
o
w
B
u
ffe
r
R
e
fr
e
s
h
C
o
u
n
te
r
R
o
w
D
e
c
o
d
e
r
C
o
l.
B
u
ffe
r
L
R
A
S
L
C
B
R
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
LDQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
2M x 16
Timing Register
UDQM
* Samsung Electronics reserves the right to change products or specification without notice.
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
K4S281632D-TI/P55
183MHz(CL=3)
LVTTL
54
TSOP(II)
K4S281632D-TI/P60
166MHz(CL=3)
K4S281632D-TI/P7C
133MHz(CL=2)
K4S281632D-TI/P75
133MHz(CL=3)
K4S281632D-TI/P1H
100MHz(CL=2)
K4S281632D-TI/P1L
100MHz(CL=3)
*I/P : Industrial Temperature (-40 to 85
°C)
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