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参数资料
| 型号： | K4S281632D-TP7C |
| 元件分类： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封装： | 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件页数： | 8/9页 |
| 文件大小： | 80K |
| 代理商： | K4S281632D-TP7C |
CMOS SDRAM
K4S281632D
Rev. 0.1 Sept. 2001
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Notes
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
1.37
4.37
Volts/ns
3
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
1.30
3.8
Volts/ns
3
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
2.8
3.9
5.6
Volts/ns
1,2
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
2.0
2.9
5.0
Volts/ns
1,2
1. Rise time specification based on 0pF + 50
to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50
to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
- 55
- 60
- 7C
- 75
- 1H
- 1L
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle
time
CAS latency=3
tCC
5.5
1000
6
1000
7.5
1000
7.5
1000
10
1000
10
1000
ns
1
CAS latency=2
-
7.5
10
12
CLK to valid
output delay
CAS latency=3
tSAC
-
5
5.4
6
ns
1,2
CAS latency=2
-
5.4
6
7
Output data
hold time
CAS latency=3
tOH
2
2.5
3
ns
2
CAS latency=2
-
3
CLK high pulse width
tCH
2
2.5
3
ns
3
CLK low pulse width
tCL
2
2.5
3
ns
3
Input setup time
tSS
1.5
2
ns
3
Input hold time
tSH
1
0.8
1
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
tSHZ
5
5.4
6
ns
CAS latency=2
-
5.4
6
7
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