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参数资料
| 型号： | K6T1008C2C |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128K x8 bit Low Power CMOS Static RAM |
| 中文描述： | 128K的x8位低功耗CMOS静态RAM |
| 文件页数： | 9/10页 |
| 文件大小： | 189K |
| 代理商： | K6T1008C2C |
PRELIMINARY
K6T1008C2C Family
CMOS SRAM
Revision 2.0
November 1997
8
DATA RETENTION WAVE FORM
CS1 controlled
VCC
4.5V
2.2V
VDR
CS1
GND
Data Retention Mode
CS1
≥VCC-0.2V
tSDR
tRDR
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
Address
CS1
tAW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2)
applied in case a write ends as CS2 going to low.
CS2
tCW(2)
WE
Data in
Data Valid
Data out
High-Z
tCW(2)
tWR(4)
tWP(1)
tDW
tDH
tAS(3)
tWC
CS2 controlled
VCC
4.5V
0.4V
VDR
CS2
GND
Data Retention Mode
tSDR
tRDR
CS2
≤0.2V
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相关代理商/技术参数 |
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| K6T1008C2C-B | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:128K x8 bit Low Power CMOS Static RAM |
| K6T1008C2C-DB55 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:128K x8 bit Low Power CMOS Static RAM |
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| K6T1008C2C-DB70000 | 制造商:Samsung SDI 功能描述: |
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