参数资料
| 型号： | KAD5510P-25Q48 |
| 厂商： | Intersil |
| 文件页数： | 9/31页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT CMOS 250MSPS 48QFN |
| 标准包装： | 40 |
| 系列： | FemtoCharge™ |
| 位数： | 10 |
| 采样率（每秒）： | 250M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 254mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 托盘 |
| 输入数目和类型： | * |
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KAD5510P
17
FN7693.2
May 2, 2011
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input matched to
VCM. The value of the shunt resistor should be determined based on the
desired load impedance. The differential input resistance of the
KAD5510P is 1000
Ω.
The SHA design uses a switched capacitor input stage
the sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle before
the next sampling point. Lower source impedance will result in
faster settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recommended for
optimal performance.
A differential amplifier, as shown in Figure 29, can be used in
applications that require DC-coupling. In this configuration, the
amplifier will typically dominate the achievable SNR and
distortion performance.
The current spikes from the SHA will try to force the analog input
pins toward ground. In cases where the input pins are biased with
more than 50 ohms in series from VCM care must be taken to
make sure the input common mode range is not violated. The
provided ICM value (250A/MHz * 250MHz = 625A at
250MSPS) may be used to calculate the expected voltage drop
across any series resistance.
VCM Output
The VCM output is buffered with a series output impedance of
20. It can easily drive a typical ADC driver’s 10k common
mode control pin. If an external buffer is not used the voltage
drop across the internal 20 impedance must be considered
when calculating the expected DC bias voltage at the analog
input pins.
Clock Input
The clock input circuit is a differential pair (see Figure 43).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
The recommended drive circuit is shown in Figure 30. A duty
cycle range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
A selectable 2x frequency divider is provided in series with the
clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate. This allows
the use of the Phase Slip feature, which enables synchronization
of multiple ADCs.
The clock divider can be controlled through the SPI port. Details on this
are contained in “Serial Peripheral Interface” on page 21.
A delay-locked loop (DLL) generates internal clock signals for
various stages within the charge pipeline. If the frequency of the
input clock changes, the DLL may take up to 52s to regain lock
at 250MSPS. The lock time is inversely proportional to the
sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
illustrated in Figure 31.
FIGURE 27. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
ADT1-1WT
0.1F
KAD5512P
VCM
ADT1-1WT
1000pF
FIGURE 28. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
ADTL1-12
0.1F
KAD5512P
VCM
ADTL1-12
1000pF
KAD5512P
VCM
0.1F
0.22F
69.8
49.9
100
348
CM
217
25
69.8
FIGURE 29. DIFFERENTIAL AMPLIFIER INPUT
Ω
FIGURE 30. RECOMMENDED CLOCK DRIVE
TC4-1W
200pF
200O
200pF
CLKP
CLKN
1000pF
Ω
SNR
20 log10
1
2
πfINtJ
-------------------
=
(EQ. 1)
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| KAD5510P-50 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:10-Bit, 500MSPS A/D Converter |
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| KAD5510P-50Q72 | 功能描述:IC ADC 10BIT 500MSPS SGL 72-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:FemtoCharge™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
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