参数资料
型号: KAD5512P-12Q72
厂商: Intersil
文件页数: 15/36页
文件大小: 0K
描述: IC ADC 12BIT 125MSPS SGL 72-QFN
产品培训模块: High-Speed Analog-to-Digital Converters
标准包装: 1
系列: FemtoCharge™
位数: 12
采样率(每秒): 125M
数据接口: 串行,SPI?
转换器数目: 1
功率耗散(最大): 235mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 72-VFQFN 裸露焊盘
供应商设备封装: 72-QFN(10x10)
包装: 托盘
输入数目和类型: 1 个差分,单极
KAD5512P
22
FN6807.4
October 1, 2010
In an application where CSB was kept low in sleep
mode, the 150s CSB setup time is not required as the
SPI registers are powered on when CSB is low, the chip
power dissipation increases by ~ 15mW in this case.
The 1ms wake-up time after the write of a ‘001x’ to
register 25 still applies. It is generally recommended to
keep CSB high in sleep mode to avoid any unintentional
SPI activity on the ADC.
All digital outputs (Data, CLKOUT and OR) are placed in a
high impedance state during Nap or Sleep. The input
clock should remain running and at a fixed frequency
during Nap or Sleep, and CSB should be high. Recovery
time from Nap mode will increase if the clock is stopped,
since the internal DLL can take up to 52s to regain lock
at 250MSPS.
By default after the device is powered on, the operational
state is controlled by the NAPSLP pin as shown in Table 3.
The power-down mode can also be controlled through
the SPI port, which overrides the NAPSLP pin setting.
Details on this are contained in “Serial Peripheral
Interface” on page 24. This is an indexed function when
controlled from the SPI, but a global function when
driven from the pin.
Data Format
Output data can be presented in three formats: two’s
complement, Gray code and offset binary. The data format
is selected via the OUTFMT pin as shown in Table 4.
The data format can also be controlled through the SPI
port, which overrides the OUTFMT pin setting. Details on
Offset binary coding maps the most negative input voltage
to code 0x000 (all zeros) and the most positive input to
0xFFF (all ones). Two’s complement coding simply
complements the MSB of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current
bit position and the next most significant bit. Figure 33
shows this operation.
Converting back to offset binary from Gray code must be
done recursively, using the result of each bit for the next
lower bit as shown in Figure 34.
Mapping of the input voltage to the various data formats
is shown in Table 5.
TABLE 3. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
TABLE 4. OUTFMT PIN SETTINGS
OUTFMT PIN
MODE
AVSS
Offset Binary
Float
Two’s Complement
AVDD
Gray Code
FIGURE 33. BINARY TO GRAY CODE CONVERSION
10
11
9
0
1
BINARY
10
11
9
0
GRAY CODE
1
FIGURE 34. GRAY CODE TO BINARY CONVERSION
10
11
9
0
1
BINARY
10
11
9
0
GRAY CODE
1
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT VOLTAGE
OFFSET BINARY
TWO’S COMPLEMENT
GRAY CODE
–Full Scale
000 00 000 00 00
100 00 000 00 00
000 00 000 00 00
–Full Scale + 1LSB
000 00 000 00 01
100 00 000 00 01
000 00 000 00 01
Mid–Scale
100 00 000 00 00
000 00 000 00 00
110 00 000 00 00
+Full Scale – 1LSB
111 11 111 11 10
011 11 111 11 10
100 00 000 00 01
+Full Scale
111 11 111 11 11
011 11 111 111 1
100 00 000 00 00
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