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参数资料
| 型号： | KIT908EINTFC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 15/49页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL 908E625 QUAD W/MCU/LIN |
| 标准包装： | 1 |
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Analog Integrated Circuit Device Data
22
Freescale Semiconductor
908E625
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
INTERRUPT MASK REGISTER (IMR)
Hall-Effect Sensor Input Pin Interrupt Enable Bit (HPIE)
This read/write bit enables CPU interrupts by the Hall-
effect sensor input pin flag, HPF. Reset clears the HPIE bit.
1 = Interrupt requests from HPF flag enabled
0 = Interrupt requests from HPF flag disabled
LIN Line Interrupt Enable Bit (LINIE)
This read/write bit enables CPU interrupts by the LIN flag,
LINF. Reset clears the LINIE bit.
1 = Interrupt requests from LINF flag enabled
0 = Interrupt requests from LINF flag disabled
High Temperature Interrupt Enable Bit (HTIE)
This read/ write bit enables CPU interrupts by the high
temperature flag, HTF. Reset clears the HTIE bit.
1 = Interrupt requests from HTF flag enabled
0 = Interrupt requests from HTF flag disabled
Low Voltage Interrupt Enable Bit (LVIE)
This read/write bit enables CPU interrupts by the low
voltage flag, LVF. Reset clears the LVIE bit.
1 = Interrupt requests from LVF flag enabled
0 = Interrupt requests from LVF flag disabled
High Voltage Interrupt Enable Bit (HVIE)
This read/write bit enables CPU interrupts by the high
voltage flag, HVF. Reset clears the HVIE bit.
1 = Interrupt requests from HVF flag enabled
0 = Interrupt requests from HVF flag disabled
Over-current Interrupt Enable Bit (OCIE)
This read/write bit enables CPU interrupts by the over-
current flag, OCF. Reset clears the OCIE bit.
1 = Interrupt requests from OCF flag enabled
0 = Interrupt requests from OCF flag disabled
RESET
The 908E625 chip has four internal reset sources and one
external reset source, as explained in the paragraphs below.
Figure 11 depicts the internal reset sources.
RESET INTERNAL SOURCES
Autonomous Watchdog
AWD modules generates a reset because of a timeout
(watchdog function).
High Temperature Reset
To prevent damage to the device, a reset will be initiated if
the temperature rises above a certain value. The reset is
maskable with bit HTRE in the reset mask register. After a
reset the high temperature reset is disabled.
Low Voltage Reset
The LVR is related to the internal VDD. In case the voltage
falls below a certain threshold, it will pull down the RST_A pin.
Register Name and Address: IMR - $04
Bits
7
6
5
4
3
2
1
0
Read
0
HPIE LINIE HTIE LVIE HVIE OCIE
0
Write
Reset
0
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